Ed’s Threads 061020Musings by Ed Korczynski on 20 October 2006Future of ICs Seen in Belgium
The beautiful tree-covered campus of the Katholieke Universiteit Leuven is the site of IMEC. I visited the Flemish research institution for its annual progress review meeting and to hear about the first major reorganization in its 20 year history. Partly driven by its growth to approximately 1500 permanent staff and visiting researchers, the re-org primarily aims to break down the conceptual walls between manufacturing technology development, multi-chip packaging, and circuit design. The three formerly independent divisions will be led by Luc Van den hove after being promoted to COO
of the new org starting in January.
There are many technical challenges in all three areas, and IMEC thinks that greater overall efficiency will come from keeping all three focused on specific targets. Through materials engineering of transistor gates, contacts, and isolation, we already provide different Vt and leakage levels. A designer can already chose from many embedded memory types. Targeted options for specific applications will increase the number of options, and the shear number of possible combinations will grow exponentially. As an example of a targeted application, finFETs
could have advantages over planar transistors for applications in analog, RF, and even embedded-SRAM.
Smaller was almost always better during the era of “simple scaling”: faster, cheaper, and indeed smaller. In the nanometer era, however, area, power/speed, and leakage are now tradeoffs. For example, a recent nano-scale IC designed by IMEC had a target speed of 500MHz at 100mW power consumption, and 95% of the first silicon chips did function. However, due to unpredictable variability in real-world transistors, only 58% of the yielding chips could function at 500MHz or faster, and just 24% consumed less than 100mW at desired speeds, for a final functional and parametric yield of only ~14%.
Some manner of new EDA capability will be needed, just as logic synthesis was added to EDA tools to handle a previous jump in design complexity. Hugo De Man, IMEC Senior Fellow, noted that, “Today we have statistical timing analysis, but not statistical timing synthesis. There is work in this direction, but no movement yet to integrate this into a standard design flow, and it will probably take seven years. It is possible to come up with a methodology that allows you to keep working as we have in the past, but we must have another level of abstraction, and that has not happened yet.”
Until new EDA tools are developed, cross-functional teams like those being established at IMEC will be needed. Designers don’t necessarily need to go back to school to study materials science, and Fab-folks don’t have to become capable of performing advanced logic synthesis, but it truly helps to at least understand the terminology and the basic work-flows of each side. For at least the next seven years, such conceptual bridging will be essential for the creation of nano-scale ICs.
IMEC wants to call all of this “Technology Aware Design” (TAD), since basic awareness of interactions between manufacturing technologies will be essential for the design of nano-scale ICs. As a word-smith, I approve of their accurate term for a complex issue, but since it is at odds with the flood of “DFM” marketing hype generated in the last few years, the term is unfortunately doomed from the start. No matter what term you chose, the work only gets more complicated and organizations like IMEC will be vital to the future of the IC industry. Much of the IC’s future is now routed through Leuven, Belgium.
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061020: Future of ICs Seen in Belgium