Ed’s Threads 070105Musings by Ed Korczynski on 2007 January 05Infineon doesn’t fancy 45nm finFETs
I’ve got fins on the brain these days.
My Dec. 8 blog entry covered finFET information presented at IEDM 2006
which included the common consensus that they would not be ready or needed for 45nm. Then I interviewed Dr. Klaus Schruefer, principal scientist for CMOS devices at Infineon Technologies, and wrote in my Dec. 15 blog entry that “Infineon fancies 45nm finFETs” for LSTP circuits
A representative from Infineon subsequently contacted me to say that I’d mistakenly read between the lines in Dr. Schruefer’s comments, and that Infineon agrees with the rest of the industry that finFETs will not be used for 45nm node low-standby power (LSTP) circuits.
Infineon still asserts that for state-of-the-art LSTP digital circuits, finFETs provide equivalent performance to planar transistors with 1/10th the leakage current, the costs of manufacturing are nearly identical, and these chips should consume one-half the battery power. However, Infineon insists that, “there is still a long way to go to adopt such a revolutionary technology. One has to demonstrate manufacturability at 32nm dimensions.”
Since any fundamentally new manufacturing technology is expensive to develop, companies need to be able to deploy the technology over many nodes to recoup the investment. However, proving manufacturability can lead to a logical Catch-22: you can’t use it until you know it will work, but you don’t know it will work until you use it.
There is always risk in anything new, but there are also rewards. The decision on whether to accept a new manufacturing risk depends on the anticipated rewards, and the only way to estimate those is to rely upon approximations and models from R&D; tests. There’s an old concept in manufacturing that you should never accept any risk unless the promised reward is substantial—such as at least doubling a fundamental metric like yield or performance.
Infineon has shown that for nearly equivalent manufacturing costs (certainly only modelled estimates at present) they can use finFETs for LSTP chips that should consume ½ of the battery power. Consumers don’t care about transistor architectures, but they sure care about battery life in cellphones, portable game players, PDAs, and iPods. Yes, displays suck battery life too, but chips dominate in many cases.
How great are the risks associated with transitioning from “planar” transistors to finFETs? There could be utterly unprecedented yield losses due to currently unfathomable interdependencies. There could be problems with metrology for in-line process-control of new structures. Any number of issues could arise. Yet if relatively standard unit-processes are combined into new process modules, and the estimated manufacturing cost is <3% greater than a baseline, then it’s hard to imagine intractable yield issues.
The current consensus is that finFETs may be first used at the 32nm node. But if they provide double the battery life for portable MP3 players, then why not deploy them earlier at 45nm? Is it really already too late to choose a new 45nm LSTP transistor manufacturing technology? Or are many companies secretly planning to deploy finFETs for 45nm LSTP, while they all publicly proclaim the opposite? Is this a key new strategic inflection point? I’m open to the possibility. As Intel’s Andy Grove has said, “Only the paranoid survive.
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070105: Infineon doesn't fancy 45nm finFETs