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061110: Wafer-level packaging in the 3D present
Ed’s Threads 061110

Wafer-level packaging in the 3D present
Wafer-level packaging (WLP) may finally reach the mainstream for ICs, according to industry vendors and analysts at the 3rd annual International Wafer-Level Packaging Conference held Nov. 1-3 in San Jose. Among the many presentations on WLP, packaging leader Amkor showed that this technology will soon be applicable to ~85% of all ICs by unit volume, and should see market growth of 25% CAGR over the next five years. Analysts presented details of the markets and applications driving this slow revolution in mainstream packaging.

In recent years, WLP has been applied to relatively small chips with <20 pins. However, larger chips tended to have mechanical reliability problems associated with the differences in thermal expansion coefficients between silicon ICs and the PCBs to which they mount. Now, new WLP technologies coming online early next year should allow for reliable WLP of up to 100-pin devices without underfill.

WLP can be attractive due to both area and cost. Since most WLP is also chip-scale, where the “die is the package,” the package can’t really get any smaller in 2D. Amkor showed that the final package size for a 7x7mm die with 208 I/O pins can be reduced >93% from that needed for a PQFP. The company also says that the price can now “be very competitive” with traditional package types, so the 2D area savings is probably the greatest advantage. Many cell phones and portable game players already incorporate WLP chips, following the lead set by Casio and Amkor to develop WLP for watches in 2004. Tessera’s ShellCase process for cell phone camera chips is also WLP.

Beyond 2D considerations, the world is now actively developing technologies to allow for 3D packaging using through-silicon vias (TSV). Samsung has shown samples of an eight-layer stacked package, and is working on a 16-layer version. Fraunhofer-IZM continues to lead the world in basic research into WLP and TSV concepts.

Both organizations are part of a new 3D packaging consortium, the semiconductor Equipment and Materials Consortium for 3D (“EMC-3D”), founded to further TSV for 3D stacking of chips in packages, by developing processes for creating 5-30µm diameter vias through 50µm thinned 300mm diameter wafers using both via-first and via-last techniques. Major processes being integrated include via etch and laser drill, insulator/barrier/seed deposition, micro-via patterning with RDL capabilities, high aspect ratio copper plating, carrier bonding, sequential wafer thinning, backside insulator/barrier/seed deposition, backside lithography, backside contact metal plating, chip-to-wafer placement and attach, and dicing. The cost of ownership (COO) goal for the integrated 3D process is $200/wafer.

EMC-3D founding member Semitool explains that each customers’ copper electroplating process to fill the TSVs is relatively unique. With diameters of 5-30µm and depths 10-50µm for different customers, there is no one generic process that can cost-effectively fill all possible vias without seams or voids.

Once TSVs are formed and wafers are thinned, the actual stacking may occur at either the chip- instead of wafer-level. 3D WLP requires near perfect yield of all chips on all wafers to ensure decent final yield, while chip-level stacking allows pick-and-place tools to work with normally yielding wafers. Singulation into individual chips may be performed with a dicing saw, laser cutting, or plasma-etching through a mask. Laser-cutting and etching may be relatively affordable if the final silicon wafers are thinned to ≤50µm, and may provide some flexibility in process integration.

WLP -- whether featuring TSVs or not -- is finally moving into the mainstream for chips. No longer just for small chips with few I/Os, WLP is now being used for dense memory stacks, integrating sensors with logic, and general system-in-package (SiP) designs.

E.K.

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061110: Wafer-level packaging in the 3D present

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061027: Applied HKMG ready when you are
Ed’s Threads 061027
Musings by Ed Korczynski on 27 October 2006

Applied HKMG ready when you are
The IEEE and Applied Materials co-sponsored a one day seminar on High-K dielectrics and Metal Gates (HKMG) yesterday in San Jose. Researchers from AMD, Freescale, IBM, Toshiba, Xilinx, and SEMATECH presented their experiences with integrating HKMG materials into CMOS transistors, and showed that these newer materials are ready for low-standby power (LSTP) IC applications. Within the last few years, the industry has converged on Halfnium-silicon-oxynidride (HfSiON) for the dielectric, and tantalum alloys for the NMOS MG. Expect to see the PMOS electrode material—likely either a titanium or tungsten alloy—emerge within the next 6 months.

Just down the street from the Winchester Mystery House in San Jose is the ostentatious nouveau-riche shopping mall they call Santana Row (even though it has no connection to Carlos). In the middle of Santana Row you find the glaring excess of the Hotel Valencia, with its faux-pan-asian-post-modern-hyper-cool-a-go-go interior design. Some of the beautiful people who normally frequent the ultra-lounges were understandably confused to see socially awkward technologists blightening the space. They had no way of knowing that we were there to discuss the latest chip technologies inside the iPods, camera-phones, and colored wall lights that make the ultra-lounges so ‘ultra.’

Consumer applications now drive IC manufacturing technology development, unlike past eras driven by government or corporate buying. New chips must meet ever tighter market windows with huge initial production volumes. New manufacturing technology brings risks, yet manufacturing high volumes of complex consumer products makes you risk-averse, so the global industry only changes technology when it sees no way other way forward.

Tom St. Dennis, Senior Vice President, General Manager Etch, Cleans, Front End and Implant Products Business Groups for Applied Materials, in an interview with SST stated that Applied has been supporting HKMG for 45nm node LSTP applications at customer sites for at least a year. St. Dennis stated, “However, there’s another dimension to all of this: cost. It used to be technology at any cost. But with consumers driving the industry today, more than ever we’re sensitized to bring our products forward with a reasonable cost target.”

Unit process development has already solved many HKMG physics-based issues such as carrier scattering, metal work-function control, and device structure scaling. Gary Miner, CTO for the Front End Products Group of Applied Materials informed SST editors that, “When we started this there were some pretty fundamental issues such as getting band-edge targets that hold at temperature. Now the integration continues across all applications.”

The bottom line is that HKMG CMOS chips are already here; Samsung is already using a halfnium-based dielectric with MG for DRAM, and has announced plans to use the materials for pseudo-SONOS Flash memory by 2008. The consensus is that high performance (HP) logic will probably not use HKMG until the 32nm node. The processes and manufacturing hardware for both HK and MG could have been deployed by now, but strain and other engineering tricks extended the capability of SiON/Poly-Si materials, which delayed the tough integration work now occurring.

Basic R&D; of high-k dielectrics and metal gates for transistors was first reported at Materials Research Society meetings well over 10 years ago. Companies like Applied Materials have developed capable tools for the introduction of these newer materials into high-volume chip manufacturing. Design tools still need to be modified, and a sufficient number of wafers must be run to establish variability values for any EDA tools. The decision to implement HKMG—as is almost always the current case—now simply hinges on the cost of manufacturing the new ‘ultra.’

– E.K.

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061027: Applied HKMG ready when you are

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.