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061215: Infineon fancies 45nm finFETs
  • Ed’s Threads
    Musings by Ed Korczynski on December 15, 2006

    Infineon fancies 45nm finFETs
    Based on the presentations at the IEEE International Electron Devices meeting (IEDM) 2006 last week, my prior Ed’s Threads entry concluded with the sentence, “Fins function for both CMOS logic transistors and floating-body memory cells, but they still aren’t likely to be seen before the 32nm node.” Confirming this assessment, representatives from AMD, IBM, Intel, and TI participating in a Tuesday night panel discussion sponsored by Applied Materials all agreed that finFETs will not be needed and therefore not used before the 32nm node.

    Dr. Klaus Schruefer, Principal Scientist for CMOS Devices of Infineon Technologies, has a different perspective. In an exclusive telephone interview with SST and WaferNews today, he explained that for 45nm low-standby power (LSTP) SoC applications, finFETs provide equivalent performance to planar transistors with 1/10th the leakage current. Work was done at IMEC and Infineon on “spacer defined fins” to relax the lithography while doubling the fin pitch. The costs of manufacturing are nearly identical, and these chips should consume one-half the battery power.

    Infineon has the system-level perspective to think about the pros and cons of different transistor architectures for SoC designs. “What is most important is not to demonstrate this on a single device, but to do it on a circuit level,” explained Schruefer. “Our products are based on SoC, so analog, RF, digital, I/O, and all modules will work based on a system-on-chip integration.” Infineon has shown logic and memory finFETs in the past, and they plan to show RF finFET circuitry as part of a full chip SoC at the VLSI Symposium 2007.

    Comparing relative processing complexity of finFETs to 45nm “planar” transistors, the use of raised source/drain regions, selective epitaxy, and complex STI have already made devices not-so-planar. However, Infineon found finFETs to be within 2-3% of planar in terms of overall process complexity. “Going down the road I think it’s a wash,” said Schruefer.

    Among the inherent advantages of fins compared to planar FETs: there are no latch-up concerns, no well implants, and no N+-to-P+ spacing concerns, so the circuit can be tightened. “We have our own test structures and our own methodology, and for analog we see a huge improvement in the intrinsic gain,” said Schruefer. “With the right dielectric and the right fin thickness you can really achieve the theoretical performance limits.” Infineon has worked with hafnium-based high-k dielectrics and fin thicknesses ~2/3 of gate length.

    The lower the drain-induced barrier lowering (DIBL) the better the circuit performance, and fin structures have 4 to 5 times lower DIBL. “Today, a bulk planar device has a DIBL of ~200 mV/V for a 40nm gate length, while we measure between 30 and 40 mV/V on our devices and it’s very stable,” informed Schruefer. “The linear currents are very important for all circuits today. Even for digital ‘stacked circuits’ with NAND and NOR, it’s not the on currents that are important but the linear current.”

    Though dual metal gates are not yet ready for high performance transistors, LSTP transistors can get by with a single in-between metal for both gates, especially if the metal is thinned to control the effective work function (EWF). With improved LSTP circuit performance at the same cost at 45nm, finFETs will certainly be used at 32nm and beyond. When dual metal gates are ready, they may be used with either planar or fin structures. “The basic message with this new device architecture,” stated Schruefer, “is that it really opens up the possibility of going further down the road.”

    —E.K.

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061215: Infineon fancies 45nm finFETs

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061212: Fabulous future for finFETs and finRAMs
Musings by Ed Korczynski on 12 December 2006

As the semiconductor manufacturing industry has moved to ever smaller device geometries, both new architectures and new materials have been under consideration. The most powerful new transistor architecture for CMOS is the finFET -- also known as multigate FET (MGFET) or trigate FET (triFET) -- which may be thought of as a thin fin of silicon around which wraps the transistor gate material. The IEEE International Electron Devices meeting (IEDM) 2006 (Dec. 11-13, San Francisco, CA) includes a lot of detailed presentations on finFETs as well as on fin structures for RAM cells.

IEDM 2006 Sessions #27 and #34 include many details of finFET integration. IMEC shows the effects of line-edge-roughness variation on mismatch in 55nm finFET SRAM arrays. SEMATECH and Freescale, IBM, TI, U. of Tokyo, and Oki Electric present work on finFETs. Samsung impressively touts a bulk finFET architecture for 40nm DRAM and beyond. Toshiba shows a high-performance logic finFET using dopant-segregated Schottky source/drain technology to achieve 960uA/µm electron drive current with leakage current in the off state of 100nA/µm for fins with both widths and gate lengths of 15nm.

Reliability tests are critical to ensure that what looks good in a lab will keep looking good out in the real world. Samsung shows a finFET structure for NAND flash memory with gate length of 63nm using TaN gate and fin width of 25nm. After 5K program/erase cycles at 200°C over two hours, the finFET memory cell drive current is 3x greater and the memory window is improved 43% compared to a planar structure using the same materials.

Nanowires can be seen as the ultimate 3D structures for transistors, with the gate all around (GAA) the channel. Two papers from the Institute of Microelectronics and CEA-LETI demonstrate vertically stacked, GAA arrays of “nano-beams” -- LETI’s array shows 6x more current flow compared to a planar transistor using the same contact area.

In an exclusive interview with WaferNEWS, Mike Mayberry, Intel’s director of components research and VP of its Technology and Manufacturing Group, explained that many chips today use a lot of embedded memory and even more will be needed going forward. On-die caching memory needs to be significantly faster than main memory access, and dense enough to hold sufficient code and data. Starting from the manufacturing steps needed to form finFETs, Intel cut off the tops of the fins so that the remaining two sides form double-gates to control charge storage in a floating-body cell. Intel calls this “Independently controlled Double-Gate Floating-Body Cell” (IDG FBC) memory -- but I prefer the far less accurate yet infinitely more memorable term “finRAM.”

Tied to the finFET manufacturing process flow, Intel will use finRAM cache when it uses finFETs for logic, which will not happen before the 32nm node. Regarding extendibility, Mayberry says that “We’ve patterned stuff down to 10nm.” Memory cells built to date have been on SOI wafers, but Intel is still comparing the cost-performance trade off with bulk silicon.

The move from 2D to 3D structures for mainstream CMOS has already occurred with elevated source/drain, and a 3D fin formation process module can be similar in complexity. Fins function for both CMOS logic transistors and floating-body memory cells, but they still aren’t likely to be seen before the 32nm node. -- E.K.

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061212: Fabulous future for finFETs and finRAMs

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.