Ed’s Threads 070420
Musings by Ed Korczynski on April 20, 2007

Solar cheerleading for fun and profit
Mike Splinter, president and CEO of Applied Materials (AMAT), is a great solar cheerleader, and he rightly urges us to consider the energy future for our children and grandchildren. In a recent presentation organized by the Commonwealth Club in Silicon Valley, he stumped for US government tax incentives for solar energy investments, and proposed that 25% of new government demand for electricity should be met by renewable sources such as photovoltaic (PV) panels.

Splinter is not merely a visionary altruist in these matters, since thin-film PV represents the next major growth opportunity for his company. As the IC manufacturing industry has matured, AMAT’s previous 20% annual growth has slowed to ~10% and new high-growth markets are needed to increase growth forecasts back to historic “outperform” levels.

AMAT has made significant investments over the last decade to acquire companies with technologies that support general manufacturing: metrology, gas-effluent abatement, and computer-integrated manufacturing (CIM) software and manufacturing execution systems (MES) for managing lots of substrates and shuttling lithographic reticles around. In addition, AMAT built the “Mayden Technology Center” as a showcase for selling special integrated process recipes in addition to the free general recipes included with all new hardware.

Semiconductor manufacturing fabs want to control their own technologies and supply chains, so they’ve paid for processes from other fabs but almost never from an equipment supplier. Solar cell manufacturing lines require relatively less technology but more classic industrial engineering, and buying an integrated and committed process along with a turn-key physical production line makes a lot of sense. In addition to general thin-films manufacturing technology, AMAT has deep experience with handling the largest FPD substrates in the world through its subsidiary Applied-Komatsu Technology (AKT).

“The latest generation of our tools can pattern six 50” TVs on a glass substrate,” almost the size of a garage door, Splinter told the Commonwealth Club audience. “With innovation we can provide an inflection point for solar energy, to make solar competitive with all other sources of electricity generation,” he championed, and suggested that his company’s technologies may lead to 2x-4x cost-reductions in thin-film PV manufacturing.

Solar sources currently provide <0.1% of the 5 TeraWatts of energy used globally each year. A trillion US$ will be spent on new electricity generation capacity worldwide in 2007, and an average 1GW-capacity coal plant emits as much CO2 as 1 million cars. Today in the US, all renewable energy is only 2% of the total. “The planet’s clock is ticking, and I hope that that ticking is the heartbeat of the planet and not something much worse,” said Splinter.

AMAT is working to set up solar panel fabs for customers in China, India, and Spain, which together represent 20% of the world’s new PV manufacturing capacity. In 2006, the solar manufacturing industry added 2GW capacity to bring the world up to 8GW total; by 2010, a $50B forecast annual investment should build total manufacturing capacity to 25GW. If just 5% of the new demand forecast for electricity worldwide would be met by solar, it would require a total $150B investment. All forecasts for future PV demand are “insatiable” for both the near- and long-term. If you're looking to invest a billion dollars somewhere, a turn-key thin-film PV manufacturing line from AMAT seems like it would provide a solid return on investment (ROI).

Specific public policy changes to help solar investment include extending the home income-tax credit, establishing a net metering law at the federal level, and mandating that 25% of electricity consumption by governments should be from renewable sources. “America is behind the rest of the world in solar energy adoption, and that’s just not acceptable. What are we waiting for?” asked Splinter, “I think you’ll agree that we have to stop making excuses.”

— E.K.

Labels: electricity, energy, manufacturing, photovoltaic, PV, solar, thin-film

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070420: Solar cheerleading for fun and profit

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Ed’s Threads 070413
Musings by Ed Korczynski on April 13, 2007

MRS meeting specs the future
The Materials Research Society (MRS) spring meeting was in San Francisco April 9-13, and the near- and far-term possibilities for process technology in our industry were presented to a record numbers of attendees. Researchers showed results from the world’s leading labs for electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes. It’s like sipping from a firehose, unless you’re interested in just one of the 36 parallel sessions.

Sachin Joshi of UT-Austin showed that hybrid-orientation technology (HOT) silicon wafers based on the MEMC direct silicon bonding (DSB) approach contain inherent defect-rich junctions between orientations. Shallow-trench isolation (STI) regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Non-silicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.

Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8 x 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.

An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel's Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.

Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties—elastic response (including lateral coupling across the pad), slurry transport, and average asperities—he showed how chip-scale uniformity can now be predicted.

Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria-slurries. A counter-intuitive “slow start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5X lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.

MRS meetings also cover wilder technologies like superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of sea-shells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.”

— E.K.

Labels: electronics, materials research, modeling, nano, self-assembly, silicon

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070413: MRS meeting specs the future

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Ed’s Threads 070406
Musings by Ed Korczynski on April 06, 2007

Turn-key fabs for India
The tide has turned, and it looks like India will finally be joining the club of fab-ed nations. Hindustan Semiconductor Manufacturing Corp. (HSMC) has partnered with Infineon to build at least two fabs in Hyerdabad, with first silicon planned for 2009. The first 200mm fab will run 130nm CMOS processes and cost ~$1 billion, and the second 300mm fab will cost US$3.2-$3.5 billion. Infineon will also license its design libraries for ICs targeting mobile phones, ID cards, and automotives.

Infineon touts its record of going from cornerstone of the fab to first-wafer-out in under one year in Malaysia, so it has set a clear precedent for successful greenfield fabs in previously undeveloped regions. However, with several other previously proposed Indian fabs abandoned, many analysts currently doubt the likelihood of success of HSMC. TI recently said no to building a fab in India, and Intel, though courted by India, chose China for a new 90nm logic fab. Many analysts site “infrastructure” issues as the primary obstacles for fabs in India, contrasted to Intel’s choice of China as a more viable region today.

In comparing India to China in this regard, I take a longer term perspective and see that India may be today where China was just 10 years ago. When the PRC started Project 909 in 1997 as part of their 9th five-year-plan, it was the first 200mm submicron fab in the country, and many people questioned whether it could succeed given the perceived problems with the infrastructure. In particular, Shanghai has had electrical power supply problems with black-outs and brown-outs common for the last decade as it grew factories at a frantic pace. Yet the government understood that power loss to a fab causes greater problems than simple downtime, and it set the priority that semiconductor fabs will always get power.

All you really need to keep a fab running is a road to an international airport, water, electricity, and mostly clean air (and the outside air has to be seriously bad to make a difference—i.e., the 1997 massive forest fires in Indonesia that messed up fabs in Singapore). If a government is motivated to set priorities, then it can all be established in a year or two.

For example, the original Motorola MOS-17 fab, now owned and operated by SMIC, was built in Tianjin, China, which is separated from the international airport in Beijing by a mountain pass regularly closed by snowfall in the winter. With priority snowplows, the road closes for at most one or two days to keep supplies running. Similarly, water can be prioritized, and newer fabs can be run with more efficient reduce/reuse/recycle strategies to minimize consumption. The competition between industry, agriculture, and people for water rights remains a very politically sensitive issue, but if there’s the will there’s the way.

Incidentally, the very ground upon which the fab is built doesn’t even have to be that stable. SMIC and GSMC had to spend an extra few months and rumored hundreds of million of dollars to drive special “resistance” foundation pylons more than 100 feet deep into the marshy land of PuDong (similar to the building of the world-famous and still productive Ford Motor Company Rouge Plant over 2000 acres of “bottomland” in Dearborn, Michigan).

SEMindia has lobbied the government to provide the infrastructure needed. Hyderabad is building a new international airport—not coincidentally near Fab City, along with freeways, new power-generation, and water has been set aside. So it all seems rather do-able—if Indian leaders make it a priority.

Unfortunately, a prominent politician has reportedly dampened some fab plans by insisting that there is limited room in Hyerdabad for only 3-4 fabs instead of the 10 ultimately proposed by HSMC. It is difficult to interpret this as encouraging, though it may reflect the government’s reasonable assessment of the near-term limits to how much they can stretch the infrastructure. There are already two other fabs in the works.

SEMindia partnered with AMD to build a wafer fab that is still planned, while they have already started on a scaled down $250 million assembly and test plant. Nano-Tech Silicon India (NTSI)—a fab set up with used 200mm tools and led by a South Korean businessman—is supposed to see first silicon out this year.

SiliconIndia is a network of “non-resident Indian” (NRI) talent that may return to help launch fabs. Let’s see what happens, but I predict ultimate success for Fab City and semiconductor manufacturing in India.

— E.K.

Labels: fab, Fab City, HSMC, Hyerdabad, India, NTSI, SEMindia

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070406: Turn-key fabs for India

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Ed’s Threads 070330
Musings by Ed Korczynski on March 30, 2007

Extending the lithography-airplane metaphor
At this year’s SPIE Advanced Lithography conference, Burn Lin, senior director of TSMC's micropatterning division, invoked an extended metaphor of airplanes to explain the evolution of lithography in the semiconductor manufacturing industry. He started with 1:1 masks as propeller planes, moved to reduction steppers as jet aircraft, added double-exposure as the supersonic Concorde, and finally considered EUV as the space shuttle. In contradiction, Larry Thompson declared that EUV is the Concorde in a panel discussion at SEMICON West last year. I resolve this metaphoric contradiction by saying that EUV is neither, but is instead a supersonic sub-orbital plane. For logical consistency, then, 157nm was the Concorde.

This metaphor applies both to the evolution of technology over time, as well as to why specific technologies are used for different applications in any given moment. Propeller planes are 1:1 masks and steppers, and just as propeller planes continue to be used for short trips and small loads, 1:1 lithography tools continue to be used in packaging and non-critical exposures. Likewise, reduction steppers are jets; just as jets developed larger bodies and faster engines, reduction steppers developed faster throughputs and tighter resolutions. While the industry moved to smaller wavelengths of light to print ever smaller features with reduction steppers, the cost to image a given area of silicon continuously decreased all through the 1980s and 1990s.

Then we came upon a fundamental limit of “optical” lithography: silica glass lenses aren’t purely transparent for wavelengths below 193nm. The upper frequency limit on “light” transmission through quartz is to lithography what the speed limit of sound is to air-transport. Both are hard limits on economics, and both can be surpassed but only with great expense for niche markets. Pursuing 157nm lithography required replacing silica glass lenses with calcium-fluoride crystal lenses, and led to rumored >$500 million in calcium-fluoride investments before the economics killed the program.

Consider the economics of state-of-the art sub-sonic air travel. A Boeing 747-400 burns five gallons/mile flown on average, or about 80 miles/gallon/passenger (assuming a fairly full load of 400 passengers). In contrast, a Concorde gave just 17 miles/gallon/passenger, or 4X less fuel-efficiency. Like the Concorde supersonic jet, 157nm litho was always going to cost more than the mainstream could afford and the global semiconductor industry decided to metaphorically ground the fleet before it was even built.

Airbus is now pushing the economic limits of sub-sonic flight with new ultra-light (and expensive) materials to make an ultra-large plane that can skip stop-overs. The Airbus A380F for freight seems to be the limit: an aluminium-lithium skin on parts of the fuselage and wings, carbon-fibre in the fuselage, and high static strength Glare (glassfibre reinforced aluminium) in the fuselage. All of this results in three full cargo levels that can accommodate standard-sized palettes along with US military palettes – a major advantage for customers that have long-haul transportation contracts with the United States Air Force. The A380 with its use of new expensive materials can be compared to 193nm lithography with immersion — both require more capital investment upfront, but promise lower costs in the end. Like an A380, the cost of a 193i stepper makes sense only for big companies doing big things. If new production volumes can justify the investment, then such big new technologies can still be very cost-effective.

Like a 747-400, a 193nm dry stepper is relatively less expensive and thus makes sense for medium to big companies doing lots of different things. Just as some airline companies (whether passenger or freight) with established networks of hubs may use two 747 flights to reach a long haul destination, so too might a fab (whether logic or memory) with established design flows and hardmasks use double-exposure/double-patterning of 193nm dry to make a final nanometer-scale pattern.

Since the visible spectrum of light is roughly 380-720nm, and with 248nm termed “deep UV,” it’s quite extreme to call ~13nm “extreme UV.” It used to be termed “soft x-ray,” but since x-ray lithography (XRL) ended up with a not-so-great reputation for mainstream commercial use, when R&D; began on 13.5nm lithography no one wanted people to think about x-rays. Regardless of terms, in this extended metaphor EUV and XRL are super-sonic sub-orbital x-planes that can fly from New York to Tokyo in a few hours. Seriously cool capabilities, but who can afford them besides the military and Intel?

Most people can afford to fly in planes, jets, and sometimes helicopters. Helicopters are like EBDR in that both provide nearly boundless flexibility and precision, but are inherently too expensive for most work. Helicopters don’t need runways and can hover to drop passengers anywhere in the world. EBDR doesn’t need a mask and can write any pattern on the wafer. Just as you might fly in a jet to an area and a helicopter to reach a specific final destination, fabs may use reduction steppers for most layers and EBDR just for a few.

Just as there’s a place in the market for all of these different aircraft technologies, so too is there a place for all of the different lithography technologies. If you need ultimate precision and can afford to process just fifteen 150mm wafers per hour, then XRL is not “next-generation” but today’s technology for you. EUV may still fly for Intel. Still, reduction steppers will continue to be used for most high-volume applications in the conceivable future.

—E.K.

Labels: lithography airplane metaphor NGL EUV XRL 193i

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070330: Extending the lithography-airplane metaphor

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