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080505: When is a Memristor a ReRAM?
Ed’s Threads 080505
Musings by Ed Korczynski on May 5, 2008

When is a Memristor a ReRAM?
HP published that they are the first to have fabricated a novel circuit element first predicted in 1971 called the “memristor.” The HP authors claim that, “until now no one has presented either a useful physical model or an example of a memristor.” HP is certainly leading the world, but as one of many companies working on this technology for resistance-change random-access memory (ReRAM) applications. This spring’s Materials Research Society meeting featured an afternoon session on ReRAM with presentations by HP as well as Fujitsu, FZ Jülich, IMEC, Panasonic, and Samsung.

Antique circuit theories are rarely invoked at MRS meetings, so the focus of the ReRAM session was all about how you engineer complex atomic-layer oxide elements. Another sub-session covered organic switching elements for printable ultra-dense memories in the far future. In other memory technology, the usual suspects are still doing the same tap-dances about FeRAM and MRAM, but PRAM seems to have new momentum due to investments by Intel and ST in Numonyx and so may take over some of the mainstream.

Robert Muller of IMEC presented fundamentals of ReRAM cells based on Cu+ and Ag+ charge-transfer complexes for memory applications. Using Ag/CuTCNQ/Al structures, Cu+TCNQ- is a solid ionic conductor, and so a potential can reduce alumina to aluminum along with a corresponding oxidation of the “noble” metal on the other side. The main resistance change is expected as an interfacial effect within a few nm gap between the solid ionic conductor and the aluminum electrode, where Cu filaments form as conductors. IMEC has seen retention time of up to 60 hours so far, but theoretically this can be much higher. The integration problem is that TCNQ begins to degrade at 200°C, so another material may be needed for dense IC memories.

Z. Wei et al. of Panasonic talked about FeOx ReRAM, as first presented by S. Muraoka et al. at IEDM 2007. Fe3O4 reduces to higher-resistance Fe2O3. Both bipolar and unipolar transitions are possible, however, the bipolar high-resistance state (HRS) degrades in only ~100 hours at 85°C, while the unipolar transition retains high resistance to >1000 hours. Interestingly, the low-resistance state (LRS) of the unipolar mode shows metallic (instead of semiconducting) dependence of resistivity to temperature. Both fast switching and long retention may be achieved by combining bipolar (<100ns>1000 hours @85°C) modes.

Herbert Schroeder et al. of Jülich Forshlungszentrum (“FZ Jülich”) showed a simple stack geometry using 100nm thick Pt top and bottom electrodes with a central TiO2 layer 27-250nm thick. As produced, Pt/TiO2/Pt is insulating (in the MΩ to GΩ range) so that “electroforming” is needed. Up to 30mA is needed for the reset current with simple unipolar stacks, though HRS/LRS is ~1000 which is excellent and has been shown with read-out voltages of 0.3V over up to 80 cycles. Bipolar switching has a HRS/LRS of only ~5, but the reset current is merely 1mA and so applicable to real-world circuits. Room-temperature reactive sputtering of Ti results in polycrystalline TiO2 with columnar grains of 5-20nm dia. The possible mechanism of “forming” is the electro-reduction of TiO2 into TiO or Ti which creates oxygen ions to drift to the anode and appear as voids.

H. Kawano et al. of Fujitsu Labs (along with the Nagoya Institute of Technology) explained some of the inherent trade-offs in device properties depending upon the top electrode used with Pr0.7Ca0.3MnO3 bipolar switching material. The mechanism for bipolar switching is more complex and the switching speed strongly depends on the electrode material; using Ag or Au as the top electrode results in 100-150ns, while an easily oxidized metal such as Al or Ti results in ~1ms. Ta forms a thinner oxide which allows 100ns switching with HRS:LRS of 10 at 7V, and this ratio was maintained up to 10,000 cycles. With Pt as both electrodes they saw no ReRAM effects.

Julien Borghetti of HP Information and Quantum System Lab (IQSL) said that they use a TiO2 target to sputter ~30nm TiOx and after a forming step the HRS:LRS ratio is 1000-10,000 for bipolar switching. After formation, the HRS shows essentially no temperature dependence on the conduction, which implies that tunneling current must be responsible for the conduction. From IV curves at different temperatures and biases, it seems that most of the TiOx has parallel degenerate or metallic states which account for ~200Ω resistance which is present in both the HRS and LRS. Then there is a tunneling gap which accounts for the difference between the two states, and it seems to be <3 nm thick and consists of some defects which assist in the tunneling. Cryogenic tests down to 3°K show resonant tunneling through a degenerate gas of electrons.

More details on the HP ReRAM manufacturing process can be found in my recent SST article, “Imprint litho forms arrays for new fault-tolerant nanoscale circuits” (Solid State Technology, April 2008) which summarizes the main information the company has presented at IEDM, SPIE, and MRS conferences in the last half-year. HP has shown how cross-bar circuits built with ReRAM switches can function both as interconnects and as logic elements. The titania/platinum materials set which can provide reversible ReRAM is not ready for production, but alumina/aluminum is ready to go and can provide irreversible effects. HP Corvalis in Oregon, with its old subtractive Al metal fab, has all the processing capability needed to integrate alumina/aluminum ReRAM with traditional CMOS circuitry for FPGA applications.

Does calling the fundamental switching element in a ReRAM a “memristor” make it switch any faster or retain a state any longer? HP’s labs and fabs do great work and deserve recognition, but unless HP plans to use memristors as novel circuit elements it’s confusing to use the term for ReRAM memory arrays. One blogging circuit designer has already imaged the possibility of building large-scale analog neural networks out of memristor arrays. Now that we’ve discovered that our ReRAMs could be memristors, the next question is: what do we do with them?


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080505: When is a Memristor a ReRAM?

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Anonymous Anonymous said...

Maybe Stan (now a Bay Area radio star) should have read reference 4 in his own paper. It contains stuff like, oh, results and facts on a whole bunch of devices that walk and quack like "memristors". Other references in his paper and the Nature Materials review suggest that there are also previous models that allowed some fairly sophisticated circuit design. So, what did HP "invent", like, exactly? I think this big PR over-the-top-fest will come back to haunt the good Dr. Williams and his otherwise competent team.

Tue May 06, 11:01:00 PM PDT  
Anonymous Tarun Kansal said...

ReRAM seems to be a grear technology for future. But I m wondering what are its advantages comparing to our ongoing memory technologies??

Wed May 07, 01:15:00 AM PDT  
Blogger SST's Ed's Threads said...

In response to the comment by "anonymous," I can only say that I suspect that this PR is part of “building the new blueprint for corporate research” as directed by new HP Labs head Prith Banerjee, to convert “scientific discoveries into the marketplace.”

Wed May 07, 01:03:00 PM PDT  
Anonymous Anonymous said...

Memristor is NOT ReRAM. Typically a resistance-change memory device changes its state only above a certain threshold voltage. However, according to the equations of memristor in HP's paper, the memristance M is a function of q, which is the integral of idt. So applying low voltage is also gradually changing the state, and the resistance state should be continuous.

Wed May 07, 01:29:00 PM PDT  
Blogger SST's Ed's Threads said...

A memristor may technically never "be" a ReRAM, yet essentially identical engineered materials are used for both devices. Theoretically an analog memristor should indeed demonstrate continuous change in resistance, while a ReRAM is intended to store digital information as two or more discrete resistance levels. The control circuitry must be completely different between the two, yet the engineered oxide which changes resistance may be identical.

Wed May 07, 03:41:00 PM PDT  
Anonymous Anonymous said...

Hello anonymous - hey, same name as me (maybe we even work for the same Higher Power). The threshold thing may be a bit of a red herring as the key to memristor action is "history dependent resistance" and all of the other referenced devices possess this. But you do bring up a very good point - how can you build a memory cell, let alone an array of them, if you are using a device that does not have some kind of threshold voltage? A threshold-less device would not be a memory cell, more of a read-disturbistor. In any case, the "real" TiO2 device shown in the HP paper does have a threshold (somewhere between 0.5 and 1 volt). So I ask again, what exactly did HP invent here? A really bad memory cell or a device that has been in the literature for decades?

Wed May 07, 09:44:00 PM PDT  
Blogger SST's Ed's Threads said...

Think of it this way: how can a capacitor be the memory element of a DRAM cell? In the same manner a memristor can be the memory element in a ReRAM cell (only the capacitor leaks and so is volatile, while the memristor retains resistance and so is non-volatile). ReRAM uses the voltage-induced switching effect between high- and low-resistance states, which can be read as the 1s and 0s of digital memory.

Thu May 08, 01:11:00 PM PDT  
Blogger Marcelo said...

I found it quite unfortunate
that S. Williams et al. in their recent Nature paper have simply ignored our recent work in theoretical modeling of
the non-volatile resistive switching effect in MIM structures that use transition metal oxide dielectrics.

Our first work appeared in 2004 in Physical Review Letters, and subsequent work appeared in PRL and APL.

Contrary to their claim in the opening paragraph of the Nature paper
"... until now no one has presented either a useful physical model or
an example of a memristor.", our 2004 paper does introduce a model,
which certainly seems to have been useful as demonstrated by the over 100 citations it has received so far.

M. J. Rozenberg, I. H. Inoue and M. J. Sanchez, Phys. Rev. Lett. 92, 178302 (2004).

M. Rozenberg
[email protected]

Sat May 10, 04:14:00 AM PDT  

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070921: Flash and DRAM rule future of IC memory
Ed’s Threads 070921
Musings by Ed Korczynski on September 21, 2007

Flash and DRAM rule future of IC memory
A one-day technical symposium on “New Frontiers in Memory”, sponsored by the IEEE and Applied Materials, was held Sept. 20th at the Hotel Valencia in San Jose, CA. Amidst the ostentatious splendor of the flashy hotel, a standing-room-only crowd of technologists learned about the leading-edge of manufacturing the densest, fastest, cheapest IC memories. The takeaway theme: The two trains of DRAM and flash memory technologies have long “left the station” and unless and until they stop, other technologies such as phase-change RAM (PRAM) and magneto-resistance RAM (MRAM) will be relegated to niche applications.

Sung-Joo Hong, VP of R&D for Hynix, discussed the scaling limits of trench-DRAM technology determined by the control of subtle topography variations inside storage-node trenches. Retention time of the recess cell transistor will be challenged again with the introduction of 1.2V devices. With inherently smaller storage area and higher fields at junctions, extending current device architectures would result in excessively low retention time. The lowest equivalent oxide thickness (EOT) of 3Å in a 50:1 aspect ratio trench is not sufficient for 3Xnm node technology. Selective epitaxy and/or finFET (with p+ poly gates) are possible solutions, though DIBL is an inherent challenge for finFETs.

George Samachisa, VP of technology at SanDisk, showed that as flash capacity has improved while cost has dropped, it has come to overlap with hard disk drives (HDD) and DRAM/SRAM. With another 10x reduction in price, SanDisk projects that flash cost/bit could actually be less than DRAM. NAND flash costs ~$10/GB today, with ~$1.0/GB likely in 5-7 years time, and today's capacity of 16Gb/chip is expected to increase to 128-256Gb chips in 5-7 years. To continue scaling, the NAND and controller must work together for defect management, wear-out leveling, cell-cell interference mitigation, file/bad-block management, standard I/O, and DSP error-correction control to enable >2 bits/cell.

SanDisk has pushed five generations of technology in just as many years of production. In 2004 most production was 130nm, while by the end of this year the majority will be 70nm, and 2008 will be mostly 56nm with some 43nm in volume. Alternative NAND technologies (SONOS and TONOS) have so far not lived up to expectations, so SanDisk believes that floating gate is still the best candidate for scaling down to the 20nm technology node. Adding SONOS would allow NAND to be scaled one more node to 1Xnm, with 3D technology the likely successor.

Prof. H.S. Wong of Stanford U., formerly with IBM's T.J. Watson R&D center, discussed the bleeding-edge of “emerging memories” including change-storage, phase-change, nano-filament formation, ferroelectrics, magneto-resistance, stiction force, and mechanical deformation. Wong cautioned that any researcher observing hysteresis in physical phenomenon is tempted to claim a "new memory technology" -- but density, scalability, and manufacturing cost constraints tend to eliminate most from serious consideration.

Tom Andre, Freescale Semiconductor's head of toggle MRAM technology, explained that 0.18µm MRAM technology provides data retention of >20 years and unlimited endurance at 125°C for a 4Mb toggle MRAM running on 3.3V power supply and 26mm2 chip size (based on a 1.26µm2 cell size). The market space for fast and non-volatile memory allows for a price of US$4/Mb. Spin-torque MRAM, as opposed to the toggle variant, allows for more efficient writing based on current-density instead of energy transferred through a field. Distributions of write-currents can be a problem, particularly for the high-end where excessive currents can induce breakdowns.

PRAM seems promising, and the fact that ex-Intel-Flash-leader and CTO Stefan Lai has joined Ovonyx is encouraging, but this technology has been pushed for nearly 40 years by Energy Conversion Devices, Ovonyx's parent company. (This time for sure…) Samsung’s 512Mb PRAM in 90nm technology uses PN diodes, complex top contacts, and other unique processes on top of standard CMOS. Intel plans for PRAM production, too.

Metal-oxide memories have been shown with NiO, TiO, Nb2O5, Al2O5, Ta2O5, and Cr-doped perovskites. The exact mechanism is not clear, but some manner of conductive filament formation seems to be involved. Consequently, the on-current should be area-independent while the off-current should be area-dependent. Solid electrolytes such as Cu-WO3 and Cu-Cu2S could be used in the future, and theoretically scaled down to a single-atom between electrodes. HP’s crossbar nano-array architecture might fit into this categorization, too.

Any new memory technology must meet a market need, and must compete with DRAM and flash in terms of cost and functionality. “There’s a lot of room to scale DRAM before we need new memory technology,” said Applied Materials Fellow Reza Arghavani, in an exclusive interview with WaferNEWS. Arghavani points out that equipment companies can bring to memory manufacturing innovations that have been in use in logic fabs for generations, such as copper interconnects, epi-layers, HK+MG, and low-k dielectrics. “They have to be re-optimized and re-integrated, but fundamentally they are the same technologies,” he said. Charge-trap memories are just like HK+MG stacks, in the need for work-function engineering of the materials interfaces, he pointed out. “The physics of it is identical.”

For at least the last few nodes, logic has driven thin-films and new materials development, while memory has driven lithography development. “Flash is driving litho resolution, while overlay is currently being driven by DRAM,” clarified Rudi Hendel, Applied Materials' managing director, technology programs, in an exclusive interview with WaferNEWS.

Humans like to sort and store information, and the ever-greater ability to store data in digital form continues to spur demand for IC memory. SanDisk presented recent data (May 2007) from Gartner Dataquest that forecasted NAND bit demand will increase 40x from 2006 to 2011, with major demand for PC, mobile phones, USB, and media players. In the last ten years, flash has already replaced a host of older storage mediums (35mm film, floppy/Zip/Clik/tape drives) and is well on the way to replacing CDs and ultra-small HDD (<1.3”). The message is clear -- other promising memory technologies have a tough train to catch.


A comment (below) that this blog entry does not distinguish between stand-alone and embedded applications is certainly correct; stand-alone memory IC technology can be more easily compared in terms of cost/density/performance, while embedded applications must consider additional cost and performance increases. Such analysis is a bit beyond the scope of what can be covered in a relatively short blog entry.

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posted by [email protected]
070921: Flash and DRAM rule future of IC memory

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Anonymous Anonymous said...

A distinction has not been made between stand-alone and embedded memory.

Wed Sep 26, 12:25:00 AM PDT  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.