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060728: DFM Keeps Designers Happily Ignorant
Ed’s Threads 060728
Musings by Ed Korczynski on 28 July 2006

DFM Keeps Designers Happily Ignorant
As a manufacturing fab guy attending this week’s Design Automation Conference (DAC) at the Moscone Center in San Francisco, I came away with some insights into the differences between the Design and Manufacturing communities of semiconductor manufacturing. Despite all the talk about walls falling down, the two essential sides of the business still live in completely different worlds.

In a DAC keynote lecture, a luminary recounted the classic stereotype each side imagines of the other (my phrasings): Designers see Fab-folks as hard-hat-wearing bone-heads, while Fab-folks see Designers as air-heads skipping through fields of daisies. IMHO both impressions are loosely based on reality, since many fab engineers probably copy-exactly without thought (i.e., “We use the same cleaning process that we’ve always used.”), and many designers probably don’t understand the concept of a real limitation (i.e., “We still want the best performance, size, and price all at once.”).

Design for Manufacturing” (DFM) is supposed to be the bridge between the two worlds, and when you dig through all the hype and claims, you find that most of it applies to the mask. Just as the lithographic mask has always been the translation of abstract conceptual space into what we like to call physical reality, the processes associated with mask-making are the focus of most of what’s spun as DFM today.

There were over 40 companies at DAC this year claiming to do DFM: mask data preparation (MDP), optical proximity correction (OPC) and other reticle enhancement technologies (RET), simulation and modeling of both random “critical-area” defects (i.e., particle shorting lines) and systematic “layout-dependent” defects (i.e., CMP layer-to-layer effects shorting lines). Most DFM solutions are post-GDSII, and they entail tweaking the dimensions of individual transistor gates and interconnect lines just prior to MDP. Some cleverly built tools “maintain the designer’s intent” and fix only critical circuit paths.

From a fab perspective, much of this seems like lackadaisical designers are only now dealing with anything other than simple shrinks. How hard is it to constrain a pitch to avoid most opens and shorts between lines, or to double-check that vias will connect no matter the variation in lithography or etching, or to avoid clustering the hottest transistors all together in the same area of the chip? These sorts of DFM solutions seem pretty obvious, though I’m sure they can be daunting to implement properly and I’m sure that EDA software development engineers work very hard. But from my perspective, Designers live very spoiled and pampered existences compared to Fab-folks.

Using sub-wavelength lithography and atomic-layer depositions of thin films to make nanoscale circuits with billions of active elements across single-crystal silicon with high yield is truly amazing work. It’s tough stuff - really, really tough. By the way…hard-hats don’t fit inside bunny suits, and just sustaining one tool in a 90- or 65-nm node CMOS production line requires multiple engineering disciplines. The fundamental technology development needed for 45nm and below nodes includes strained-SOI wafers, exotic metals, and hetero-epitaxial atomic layers – requiring the extraordinarily challenging materials engineering that has been on-going for decades. The great semiconductor industry era-of-the-shrink occurred only because of continuous engineering innovations in manufacturing.

Designers don’t want to know about any of this; they want to remain completely ignorant of optical physics and materials science. EDA tools have already liberated Designers from ever having to think about the real world of gate dielectrics and metal contacts. The EDA companies continue to give their customers what they want. Now DFM promises continued happy ignorance for Designers…but someone better check on how those new models are calibrated.

— ed

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060728: DFM Keeps Designers Happily Ignorant

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.