Ed’s Threads 060811
Musings by Ed Korczynski on 11 August 2006
Pain of Knowing Beats IgnoranceLying on a table face-down, while my leg jumps like a dissected frog’s in response to electrical stimulation, I think about advanced metrology for nanometer-scale IC fabs. I also think about the bizarre pain that’s not overly intense but just feels fundamentally wrong. I don’t recommend doing an
electromyogram and nerve-conduction study unless you really think you need it, which I did, after debilitating pain from major nerve-trunks pinched by bulging disks in my lower spine.
The tests provided data, which allowed my doctor to inform me that my nerves are AOK, and that continued physical therapy should be all it takes to complete my healing. (Very good news.) The tests were painful and they took time out of my day, but they were the only way to gain direct information about what was really happening. A lot like the need for more information in leading-edge semiconductor fabs (see last week’s blog, [URL]“Knowing where your atoms be”[/URL])—some people may resist adding metrology steps because they worry about the “pain” or the time involved.
One of the most vital metrics of a semiconductor manufacturing line is the yield “ramp rate”: how fast the percentage of good chips per wafer increases over time. While mature commodity chips may yield in the 90% range, many SoCs and other leading-edge chips may have initial yields well below 50%. Since it costs the fab nearly the same amount to make the wafer regardless of yield (except for test), it’s obvious that ramping as fast as possible is the only way to go.
What holds back yield? These days, due to the concerted efforts of equipment and materials suppliers, the majority of the yield loss is not due to random particles. Things and stuff (technical terms) are really very clean today. Most yield loss today is due to
systematic issues: repeatable (not random) defects caused by narrow process windows and specific device topologies. For example, CMP dishing in a lower layer combined with lithography defocus could result in a metal via open every single time.
Systematic yield losses tend to be caused by complex interdependencies which can only be found through extensive data mining. Data that we used to be able to ignore as “2nd-order” and “3rd-order” are now critical information. Companies that accept this reality, and embrace the need for more metrology to produce more actionable information, demonstrate rapid yield ramps at 90nm and 65nm nodes.
Intel, AMD, and TSMC have all shown yield curves indicating that they’ve actually ramped faster as they’ve gone from 130nm to 90nm to 65nm, while other companies report serious problems with yield ramps. Leading companies win by understanding that the game just gets more complex and expensive, and they must invest more simply to keep playing. There will always be companies happy to be followers—many chips don’t need to be made on <180nm node lines, of course—but if you want to play at the high-stakes table, you have to make the big ante.
What does any of this have to do with the nerves in my lower back? At the risk of overly-stretching the metaphor: my pinched nerves correspond to a reduced process window (a very narrow range of pain-free motions), and my habitual movements effecting spinal-disk status are like the complex interdependencies that can degrade yield. With information on the process-window (my nerves), I can reduce guard-banding (i.e., increase movements without fear of injury), which will provide a faster ramp rate (healing). Ignorance is not bliss—it just delays meaningful improvements.
— ed
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060811: Pain of Knowing Beats Ignorance
