Ed’s Threads 060825
Musings by Ed Korczynski on 25 August 2006
Moore’s Prediction for Post-Law HOT CHIPS
Nine years ago when I
interviewed Gordon Moore, he observed that atomic limits in manufacturing will coincide with the ability to put billions of transistors on a single-chip, and that this huge number would open up completely new approaches in chip design. Such new approaches would allow new functionalities to be deployed without continued shrinks.
The
HOT CHIPS 18 conference gathers hundreds of computer scientists and system architects to exchange visions and compare notes. Reconfigurable and parallel computing advances were shown on the first day with truly revolutionary concepts in chip design and function. Ambric is a newish company with a vision for an SoC built out of a 2D array of identical “bric” units, including microprocessors, embedded memory, and cleverly conceived global interconnection hierarchy.
Each bric has eight 32-bit RISC CPUs and 13 KBytes SRAM. Brics connect by abutment through word-wide channels with several levels of hierarchy that can run at up to 10.6 Gigabits per second to form a TeraOPS computing “fabric.” The company’s first chip is an all standard-cell 130nm ASIC made in a general-purpose logic process, with 45 brics in its core array containing a total of 360 CPUs and 4.6 Mbits of distributed SRAM. They
claimed this massively-parallel 130nm chip beat a 90nm TI DSP at some benchmark…but it was probably downhill with the wind…
Connex Technology showed a fully programmable HDTV chip, while U.C. Davis showed multiple applications of asynchronous arrays of simple processors. Bernie Meyerson, IBM Fellow and Chief Technologist, provided the big picture perspective on why the limits of classic scaling call for collaborative technology development at all levels. Chips will change to decode video in any encrypted format, and software downloads would deploy new functions.
The result is that some of the current nanoscale processes may be optimized for a particular design and going to the next node may not be the easiest way to add new functionality or reduce cost. Using less exacting design rules allows for less tight integration between design and process, according to Moore (1997): “If you can back off a generation in complexity or performance, then that integration doesn’t need to be nearly as close. If the most advanced technology is not necessarily an advantage…you might as well run the old processes and the depreciated equipment.”
The first decade of the industry saw tremendous innovation, and the transistors/chip doubled every year. The rate of doubling being closer to every two years for other periods is also quite understandable, and clear atomic limits will slow it down. Moore (1997) said, “The update I did on so-called Moore’s Law in 1975 at the IEDM meeting resolved where the improvements had come from previously…we were learning to pack things more efficiently, what I called ‘cleverness.’ We went to isolationless structures, for example. I think we’re looking at the same kind of thing again. So you have the flexibility of what do you do with a billion transistors worth of circuitry. The slope will have changed again, but the industry is certainly not going to stop.”
When Moore’s Law eventually slows—despite Intel’s current 18-month pace—we’ll have billions of transistors with which to play. Hot new reconfigurable designs will exploit the sheer number of transistor to deliver new functionalities to consumers, which will keep silicon running through fabs for decades to come.
— ed
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060825: Moore's Prediction for Post-Law HOT CHIPS
