Ed’s Threads 070413
Musings by Ed Korczynski on April 13, 2007

MRS meeting specs the future
The Materials Research Society (MRS) spring meeting was in San Francisco April 9-13, and the near- and far-term possibilities for process technology in our industry were presented to a record numbers of attendees. Researchers showed results from the world’s leading labs for electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes. It’s like sipping from a firehose, unless you’re interested in just one of the 36 parallel sessions.

Sachin Joshi of UT-Austin showed that hybrid-orientation technology (HOT) silicon wafers based on the MEMC direct silicon bonding (DSB) approach contain inherent defect-rich junctions between orientations. Shallow-trench isolation (STI) regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Non-silicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.

Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8 x 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.

An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel's Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.

Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties—elastic response (including lateral coupling across the pad), slurry transport, and average asperities—he showed how chip-scale uniformity can now be predicted.

Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria-slurries. A counter-intuitive “slow start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5X lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.

MRS meetings also cover wilder technologies like superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of sea-shells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.”

— E.K.

Labels: electronics, materials research, modeling, nano, self-assembly, silicon

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070413: MRS meeting specs the future

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