Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008
Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations
at the recent International Interconnect Technology Conference IITC., some of which
I've already discussed in this blog.
What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.
New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC,
Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.
NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.
Low-
k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson
covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.
Further proving that
“there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.
An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:
- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.
The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.
With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.
New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.
There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “
living in interesting times.”
Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.
—E.K.
Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research
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080613: Process integration drives the IC industry
