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080613: Process integration drives the IC industry
Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

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071102: Leti continues to lead research
Ed’s Threads 071102
Musings by Ed Korczynski on November 02, 2007

Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is devoted to ~€300M annual micro-electronics work. The huge new Minatec fab is also on this site, and any developed technology that appears to be commercially viable will be spun out as a “baby” company; Leti has had over 30 babies so far, of which Soitec has grown up the most. Soitec and Leti still maintain close working relations, with personnel routinely spending one day each week at each others’ sites.

TraciT and PicoGiga were also Leti babies, though both have since been absorbed within Soitec. TraciT works on transferring finished device layers, using a combination of thinning with backgrinders/CMP and the Smart-Cut technique. “The Smart-Cut technique is a toolbox, not a single process,” explained Camille Darnaud-Dufour, VP of Communications for Soitec, who accompanied me on the Leti tour. Smart-cut—using hydrogen implant/anneal—works very well cutting layers up to 1μm thick, but to do 5-10μm you need some temporary bonding and wafer thinning. For the latter applications, Leti works with de-bondable SOI using handle-wafers and temporary adhesives.

Laurent Clavelier, who leads much of the work on new layer-transfer technologies such as wafer-to-wafer GeOI and InP chip-to-wafer heterogeneous integration, graciously took me on a full tour through the 200mm and 300mm fabs, which do both pure R&D and pilot production, with typically ~100 lots of wafers-in-process at any given time, running three shifts 24hrs/day during the week and half of the weekend. The fab is stuffed with standard production tools, such as Applied Materials’ implanters and CVD, ASM for epitaxial growth, Lam etchers, Semitool for ECD, Ebara for CMP, and KLA-Tencor and Veeco metrology tools.

In addition to standard CMOS fab tools, Leti has several unique tools such as a fully configured 200/300mm EVG bonder providing precise control of wafer-to-wafer alignment for work on patterned and device layer transfers. This system provides integrated single-wafer wet cleaning including a megasonic arm, and with control of bonding parameters it can perform automated designs-of-experiments. In addition to standard lithographic steppers, Leti uses e-beam direct-write with a single-beam for precise gate-length formation.

GeOI work now involves transferring not just blanket substrates, but full pMOS Ge FETs, which Clavelier claimed “is the best way to do fully depleted high-performance germanium on insulator.” Leti is also working on a “sequential front-end” process that would form nMOSFETs using strained SiGe as a first layer, and after planarization then compression bond a blanket 0.5μm thin <110> Ge layer on top. The pMOSFETs can then be formed in the transferred Ge layer since they require a maximum processing temperature of just 600°C.

GaNOI work is done in coordination with the PicoGiga people, using a combination of epitaxy and layer-transfer to aim for the highest-brightness blue LEDs. Work on optical interconnects continues for clock distribution on chip. Using indium phosphide (InP) III-V wafers to create laser diodes and detectors, thinned dice are bonded to wafers containing thin film optical waveguide structures.

Leti also pursues work on double-gate MOSFET to make high-power and low Vt devices such as 4T SRAMs. Doing so in planar structures requires the use of buried gates below transferred channel layers, so patterned layer transfer capability is enabling.

For 3D stacking applications, Leti and Minatec work with ST and the U. of Bologna on high-speed chip-to-chip communications through capacitive coupling across a silica bonding layer. Two CMOS wafers, each with nine layers of copper interconnects, can be bonded together face-to-face; one wafer is thinned, and then shallow bind-vias are formed to allow for wire-bonding down to exposed bond pads.

A very novel application of a blanket layer transfer that results in a pattern is controlled by a precise angular misalignment. A few degrees precise twist of a top wafer relative to a bottom wafer results in a crystalline mismatch that forms periodic dislocation strips. Using crystals with cubic orientations exposed on their faces can thus result in orthogonal arrays of dislocation strips with 50nm spacing, and these dislocations can be selectively etched to form orthogonal trench arrays for memory cells.

With so much exciting and ground-breaking work going on, it is a bit surprising that Leti is not more widely known for leading the industry -- though parent organization CEA is comparable to the US’ Sandia National Labs, and the culture of an organization devoted to creating weapons-of-mass-destruction is necessarily rather secretive. Even though Leti mostly pursues commercial technology development today, the legacy of secrecy continues as the default culture and the organization just doesn’t have the habit of self-promotion. Somewhat quietly then, Leti continues to lead.

–E.K.

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071102: Leti continues to lead research

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Anonymous Howard Levine said...

Ed-

I had the opportunity to participate in last Summer's EMC3D roadshow that included a stop at Leti and was very impressed with the excellent facilities in this most beautiful town of Grenoble.

Howard Levine
SemiConn Consulting
Stamford, CT

Tue Nov 13, 02:31:00 PM PST  

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070817: FEI Phenom - SEM for the people
Ed’s Threads 070817
Musings by Ed Korczynski on August 17, 2007

FEI Phenom - SEM for the people

FEI has been supplying Scanning electron microscopes (SEM) to the semiconductor industry to help inspect ever smaller circuit-elements during the decades of the shrink. Now the miniaturization in electronics enabled by SEMs has been paired with miniaturized hardware to create a small revolution in microscopy. The company's new Phenom electron microscope, the size of a large coffee maker (Fig. 1) plus a small below-table vacuum pump, requires no external vibration isolation, can load a sample in <30 seconds, and costs <$80K.

Information is power, but it’s got to be “productive information” to be useful in production. Knowing what you’ve got is critical, so cost-effective metrology and inspection tools are essential for the operation of labs as well as fabs. SEMs provide essential information from R&D; to manufacturing quality control, but they are generally slow and sensitive instruments. It takes a skilled technician many minutes to load and focus samples in expensive tools, such that “SEM time” is a common bottleneck in R&D.;
The first SEM was developed in 1961 (Fig. 2). The electronics have shunk over the decades, and analysis capabilities such as energy-dispersive X-ray microanalysis have evolved, but the basic layout and size of the electron column and vacuum chamber have remained somewhat constant. Now FEI has shown that throwing out the old playbook and starting from scratch can produce a revolution in inspection tools.

Developed for broad ubiquitous applications in science and engineering after an “ah-ha” flash of insight a few years ago, the Phenom is the first commercial tool from FEI to take advantage of a real hardware miniaturization revolution.

By shrinking the electron column down so that it actually fits in the palm of your hand (Fig. 3),



and mating it to a miniscule vacuum-chamber and sample-holder cup (Fig. 4),





the combined small mass can be so rigidly coupled that it floats free from external vibrations.

At SEMICON West this year, the company showed a working unit on top of a cheap display table. I knocked on the sides of the unit and could see the tool’s outer skin vibrating while the image from the sample inside remained rock solid (Fig. 5).
The adjacent image was taken by me as the SEM operator after just three minutes of training. (Admittedly, I did learn to run traditional SEMs as an undergrad at MIT, but such prior training is really not needed with this tool.) FEI did a great job of developing a very easy to use GUI with touch-screen control for focus, magnification to 20,000x, contrast, etc.

Beyond picking up where optical microscopes are losing resolution power, the Phenom’s potential market will also include organizations that need SEM technology but cannot afford the typical >$200,000 investment for a traditional SEM system, plus the costs of additional personnel and facilities. At approximately one-third the price of a traditional SEM, this new tool should find broad acceptance in academia as well as industry. The Phenom is now available for purchase in Europe and North America, and sales to the rest of the world will be rolled out in 2008.

Finally, I've found the perfect tool to inspect my Shure VST-III stylus tip for wear. If only I could find someone who still knew what the stylus for a vinyl turntable was supposed to look like…

—E.K.

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Blogger Becky said...

You should also look at Hitachi's TM-1000 tabletop SEM. The two are comparable; pros and cons abound for each, just as they do for the regular SEMs. The TM-1000, with a 10kV accelerating voltage, has the option for EDX and they way it is integrated is very neat. I recently spent time 'playing' with both of these tools at the recent Microscopy & Microanalysis conference in Ft. Lauderdale and wish I had one of each on my desk. I say 'playing' because I've been an SEM user/trainer for over 20 years and these SEMs are both fun and easy to use. They definitely fill the gap between optical microscopy and the higher-end SEMs.

Tue Aug 21, 03:40:00 PM PDT  
Blogger SST's Ed's Threads said...

Beth Moseley, who works on Marketing for Hitachi High Technologies America, wrote to correct the previous comment about the TM-1000. The accelerating voltage is set at 15kV on the TM-1000. Hitachi's developers felt that this was the best all around condition for most sample imaging. I haven't had a chance to see the TM-1000 in person since it's release in the US last year, but it seems like another fine tool from Hitachi.

Tue Aug 28, 11:25:00 AM PDT  

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070622: Intel researches teraflops and biochips
Ed’s Threads 070622
Musings by Ed Korczynski on June 22, 2007

Intel researches teraflops and biochips
Andrew Chien, Intel VP and director of research, provided an exclusive interview with Solid State Technology and WaferNEWS during Intel Research Day this year. Chien heads all Intel research, involving nearly 1000 people at 15 locations worldwide (three of which are at universities). “There are nearly a hundred people doing research, and nearly a thousand people doing platforms based on the research,” explained Chien. “It’s not device physics or materials science, it’s real manufacturing work.” You can now find more information at [email protected] Blog.

Chien is responsible for thinking of new microprocessors, new microprocessor applications (including those embedded), and novel fab-able devices that could retain high profit margins. Discussing novel non-silicon transistor technologies, such as printable or polymer electronics, Chien expressed that these newer technologies must find winning applications beyond what is currently served by silicon chips.

Opportunities exist in the intersection of digital CMOS fabrication technology and biological applications. Intel's Fab8 in Israel has been working on novel sensor architectures based on field-effect devices on 200mm wafers, where the quantity of specific molecules bonded to uniquely tuned sites creates a change in current flow. Think of this as similar to sticking a sensor layer to the top gate of a FET where the change in bonded molecules alters the current flow through the channel. Integration of sensor elements with CMOS circuitry in a hybrid-SoC is expected to be easily done on-chip; while sensors could be integrated with separate CMOS chips in 3D stacks, there is already sufficient “free silicon real estate” at the periphery of the sensor areas to fit in all the CMOS needed.

Intel is also trying a super-computer architecture end-run on IBM’s Blue Gene, by releasing a Teraflop multicore single chip. On display at the Research Day event was a rack with a board stuffed with very fancy metal packaging and active water-cooling loops surrounding a (reportedly) 275mm2 160-core chip in 65nm technology. This chip has been shown to perform at 1.01 teraflops @ 0.95V, 62W based on the following single-chip architecture:
1 poly, 8 Cu metal lines form a 2D mesh,
100 million transistors with dynamic power management,
80 tiles (3mm2 each) composed of dual FPMAC cores, and
Packaged with 1248 pins (343 signal) C4 and a 14 layer PCB.
Memory hierarchy for this new chip design includes private L1 memory within each core, as well as several levels of shared L2 cache. A third level of SRAM or DRAM cells will likely be integrated as a separate chip in a 3D stack to manage bandwidth requirement in integration to the overall system.

What a bunch of teraflop chips is very good at is anything “computationally intensive,” requiring extreme amounts of computing power -- for example, calculating the interacting and overlapping phases of light shifted by randomly placed sub-wavelength features across a vast 2D space, a.k.a. inverse-lithography maskmaking (see related writeup by phase-shift mask pioneer and MicroLithography World editor M. David Levenson). Yan Borodovsky and Vivek Singh showed a mask with pits etched to greater depth for longer wavelength red, so that a common laser-pointer shone through the mask would form a bit of an Intel logo on the wall. You almost have to see this hologram-like effect to believe it yourself. There is no metal to mask the light, just the phase cancellation from the pits. The fundamental capability of computationally intensive inverse lithography modeling will be key to all of Intel’s design- for manufacturing (DFM) going forward, even if the phase-pit masks enabled by the technology aren’t anticipated until <32nm.

Beyond manufacturing, Intel also researches software breakthroughs that might demand a lot of processing power. “We shifted resources to respond to the increased focus upon ‘context-dependent computing,’ where sensor data is processed to determine whether you’re eating, sleeping, or watching a performance,” explained Chien. “We can already determine human emotion based on facial gestures, and that information will be incorporated into context-dependent devices.”

With a teraflop possible from a single chip, the capabilities seem nearly endless. Ten years ago, Gordon Moore foresaw that once the atomic limits of manufacturing are reached (still a bit off, but now quite on the horizon), we’ll be in a realm of hundreds of millions of really inexpensive transistors, and clever designs will break open whole new applications for silicon chips. Chien confirms that the design mindset today does not consider the number of transistors to be a constraint, merely the inherent power consumption of those working and waiting. With clock-rates now somewhat fixed, Chien says that it’s actually much easier to work with innovation at the architectural level.

Hold on to your hats, folks—now that designer have to do more than just scaling and clock-accelerations to get performance increases, they might actually start pulling their own weight, and this industry will really take off!

—E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.