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070622: Intel researches teraflops and biochips
Ed’s Threads 070622
Musings by Ed Korczynski on June 22, 2007

Intel researches teraflops and biochips
Andrew Chien, Intel VP and director of research, provided an exclusive interview with Solid State Technology and WaferNEWS during Intel Research Day this year. Chien heads all Intel research, involving nearly 1000 people at 15 locations worldwide (three of which are at universities). “There are nearly a hundred people doing research, and nearly a thousand people doing platforms based on the research,” explained Chien. “It’s not device physics or materials science, it’s real manufacturing work.” You can now find more information at [email protected] Blog.

Chien is responsible for thinking of new microprocessors, new microprocessor applications (including those embedded), and novel fab-able devices that could retain high profit margins. Discussing novel non-silicon transistor technologies, such as printable or polymer electronics, Chien expressed that these newer technologies must find winning applications beyond what is currently served by silicon chips.

Opportunities exist in the intersection of digital CMOS fabrication technology and biological applications. Intel's Fab8 in Israel has been working on novel sensor architectures based on field-effect devices on 200mm wafers, where the quantity of specific molecules bonded to uniquely tuned sites creates a change in current flow. Think of this as similar to sticking a sensor layer to the top gate of a FET where the change in bonded molecules alters the current flow through the channel. Integration of sensor elements with CMOS circuitry in a hybrid-SoC is expected to be easily done on-chip; while sensors could be integrated with separate CMOS chips in 3D stacks, there is already sufficient “free silicon real estate” at the periphery of the sensor areas to fit in all the CMOS needed.

Intel is also trying a super-computer architecture end-run on IBM’s Blue Gene, by releasing a Teraflop multicore single chip. On display at the Research Day event was a rack with a board stuffed with very fancy metal packaging and active water-cooling loops surrounding a (reportedly) 275mm2 160-core chip in 65nm technology. This chip has been shown to perform at 1.01 teraflops @ 0.95V, 62W based on the following single-chip architecture:
1 poly, 8 Cu metal lines form a 2D mesh,
100 million transistors with dynamic power management,
80 tiles (3mm2 each) composed of dual FPMAC cores, and
Packaged with 1248 pins (343 signal) C4 and a 14 layer PCB.
Memory hierarchy for this new chip design includes private L1 memory within each core, as well as several levels of shared L2 cache. A third level of SRAM or DRAM cells will likely be integrated as a separate chip in a 3D stack to manage bandwidth requirement in integration to the overall system.

What a bunch of teraflop chips is very good at is anything “computationally intensive,” requiring extreme amounts of computing power -- for example, calculating the interacting and overlapping phases of light shifted by randomly placed sub-wavelength features across a vast 2D space, a.k.a. inverse-lithography maskmaking (see related writeup by phase-shift mask pioneer and MicroLithography World editor M. David Levenson). Yan Borodovsky and Vivek Singh showed a mask with pits etched to greater depth for longer wavelength red, so that a common laser-pointer shone through the mask would form a bit of an Intel logo on the wall. You almost have to see this hologram-like effect to believe it yourself. There is no metal to mask the light, just the phase cancellation from the pits. The fundamental capability of computationally intensive inverse lithography modeling will be key to all of Intel’s design- for manufacturing (DFM) going forward, even if the phase-pit masks enabled by the technology aren’t anticipated until <32nm.

Beyond manufacturing, Intel also researches software breakthroughs that might demand a lot of processing power. “We shifted resources to respond to the increased focus upon ‘context-dependent computing,’ where sensor data is processed to determine whether you’re eating, sleeping, or watching a performance,” explained Chien. “We can already determine human emotion based on facial gestures, and that information will be incorporated into context-dependent devices.”

With a teraflop possible from a single chip, the capabilities seem nearly endless. Ten years ago, Gordon Moore foresaw that once the atomic limits of manufacturing are reached (still a bit off, but now quite on the horizon), we’ll be in a realm of hundreds of millions of really inexpensive transistors, and clever designs will break open whole new applications for silicon chips. Chien confirms that the design mindset today does not consider the number of transistors to be a constraint, merely the inherent power consumption of those working and waiting. With clock-rates now somewhat fixed, Chien says that it’s actually much easier to work with innovation at the architectural level.

Hold on to your hats, folks—now that designer have to do more than just scaling and clock-accelerations to get performance increases, they might actually start pulling their own weight, and this industry will really take off!

—E.K.

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070622: Intel researches teraflops and biochips

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.