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071102: Leti continues to lead research
Ed’s Threads 071102
Musings by Ed Korczynski on November 02, 2007

Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is devoted to ~€300M annual micro-electronics work. The huge new Minatec fab is also on this site, and any developed technology that appears to be commercially viable will be spun out as a “baby” company; Leti has had over 30 babies so far, of which Soitec has grown up the most. Soitec and Leti still maintain close working relations, with personnel routinely spending one day each week at each others’ sites.

TraciT and PicoGiga were also Leti babies, though both have since been absorbed within Soitec. TraciT works on transferring finished device layers, using a combination of thinning with backgrinders/CMP and the Smart-Cut technique. “The Smart-Cut technique is a toolbox, not a single process,” explained Camille Darnaud-Dufour, VP of Communications for Soitec, who accompanied me on the Leti tour. Smart-cut—using hydrogen implant/anneal—works very well cutting layers up to 1μm thick, but to do 5-10μm you need some temporary bonding and wafer thinning. For the latter applications, Leti works with de-bondable SOI using handle-wafers and temporary adhesives.

Laurent Clavelier, who leads much of the work on new layer-transfer technologies such as wafer-to-wafer GeOI and InP chip-to-wafer heterogeneous integration, graciously took me on a full tour through the 200mm and 300mm fabs, which do both pure R&D and pilot production, with typically ~100 lots of wafers-in-process at any given time, running three shifts 24hrs/day during the week and half of the weekend. The fab is stuffed with standard production tools, such as Applied Materials’ implanters and CVD, ASM for epitaxial growth, Lam etchers, Semitool for ECD, Ebara for CMP, and KLA-Tencor and Veeco metrology tools.

In addition to standard CMOS fab tools, Leti has several unique tools such as a fully configured 200/300mm EVG bonder providing precise control of wafer-to-wafer alignment for work on patterned and device layer transfers. This system provides integrated single-wafer wet cleaning including a megasonic arm, and with control of bonding parameters it can perform automated designs-of-experiments. In addition to standard lithographic steppers, Leti uses e-beam direct-write with a single-beam for precise gate-length formation.

GeOI work now involves transferring not just blanket substrates, but full pMOS Ge FETs, which Clavelier claimed “is the best way to do fully depleted high-performance germanium on insulator.” Leti is also working on a “sequential front-end” process that would form nMOSFETs using strained SiGe as a first layer, and after planarization then compression bond a blanket 0.5μm thin <110> Ge layer on top. The pMOSFETs can then be formed in the transferred Ge layer since they require a maximum processing temperature of just 600°C.

GaNOI work is done in coordination with the PicoGiga people, using a combination of epitaxy and layer-transfer to aim for the highest-brightness blue LEDs. Work on optical interconnects continues for clock distribution on chip. Using indium phosphide (InP) III-V wafers to create laser diodes and detectors, thinned dice are bonded to wafers containing thin film optical waveguide structures.

Leti also pursues work on double-gate MOSFET to make high-power and low Vt devices such as 4T SRAMs. Doing so in planar structures requires the use of buried gates below transferred channel layers, so patterned layer transfer capability is enabling.

For 3D stacking applications, Leti and Minatec work with ST and the U. of Bologna on high-speed chip-to-chip communications through capacitive coupling across a silica bonding layer. Two CMOS wafers, each with nine layers of copper interconnects, can be bonded together face-to-face; one wafer is thinned, and then shallow bind-vias are formed to allow for wire-bonding down to exposed bond pads.

A very novel application of a blanket layer transfer that results in a pattern is controlled by a precise angular misalignment. A few degrees precise twist of a top wafer relative to a bottom wafer results in a crystalline mismatch that forms periodic dislocation strips. Using crystals with cubic orientations exposed on their faces can thus result in orthogonal arrays of dislocation strips with 50nm spacing, and these dislocations can be selectively etched to form orthogonal trench arrays for memory cells.

With so much exciting and ground-breaking work going on, it is a bit surprising that Leti is not more widely known for leading the industry -- though parent organization CEA is comparable to the US’ Sandia National Labs, and the culture of an organization devoted to creating weapons-of-mass-destruction is necessarily rather secretive. Even though Leti mostly pursues commercial technology development today, the legacy of secrecy continues as the default culture and the organization just doesn’t have the habit of self-promotion. Somewhat quietly then, Leti continues to lead.


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071102: Leti continues to lead research

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Anonymous Howard Levine said...


I had the opportunity to participate in last Summer's EMC3D roadshow that included a stop at Leti and was very impressed with the excellent facilities in this most beautiful town of Grenoble.

Howard Levine
SemiConn Consulting
Stamford, CT

Tue Nov 13, 02:31:00 PM PST  

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070824: Intel finds signs of heterogeneous life after silicon
Ed’s Threads 070824
Musings by Ed Korczynski on August 24, 2007

Intel finds signs of heterogeneous life after silicon
With CMOS circuits using silicon channels running into performance limitations, doping with germanium and straining the lattice have already been used to push the limits. The limits of silicon remain, though, and so compound semiconductors are again under consideration as building blocks for mainstream ICs—this time integrated on top of 300mm silicon wafers.

The first solid-state transistors were built with germanium (Ge), but Ge crystals do not grow a nice surface-passivating oxide as do silicon crystals, and the oxide is vital to prevent surface defects that would otherwise kill performance. Grown silicon oxide has been the heart of cost-effective high-volume IC production for over 40 years. Even high-k (HK) gate dielectrics based on hafnium-oxides will typically be used on top of a grown and partially etched-back silicon oxide layer.

What comes after high-k and metal-gates (HK+MG)? Heterogeneous integration of compound semiconductors will completely replace the silicon channel. Silicon wafers would still be used, but only as physical supports for different NMOS and PMOS transistor materials. The new channel materials will be deposited and/or grown using technologies such as metal-organic CVD (MOCVD), solid-phase epitaxy (SPE), and spike/flash anneals.

Though HK+MG has been spun as the biggest change in 40 years, when compound semiconductors are integrated with silicon it will be a far greater integration challenge for it will require an even greater number of new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.

This summer, Intel researchers achieved success at fabricating high performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. On their internal blog, they show curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.

Mike Mayberry, Intel’s director of components research, has articulated five general areas of research and develop needed to create a competitive commercial heterogeneous semiconductor fab technology:
1) put compound semiconductors on silicon wafers,
2) find different high-k dielectrics for the gates,
3) develop PMOS materials to go with known NMOS,
4) develop enhancement-mode devices instead of depletion-mode, and
5) “Make them small enough to compete with silicon transistor densities.”

The last is the tricky part. These circuits are conceived of as being possible at or past the 22nm node, so that means high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.

By the time InSb and InGaAs could be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. In an email exchange with me after his initial blog posting, Mayberry answered some questions relating to finFETs as possible structures for heterogeneous integration. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate and thus, that builds pressure to find a vertical solution for III-V,” he confirmed, but he admitted that, “we do not as yet have a solution to that problem.”

If finFETs are used, new metal alloys will need to be developed to be able to form minimal resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.

In my email exchange with Mayberry, he confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows—and will let us know—is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.

This is all starting to get into some serious materials engineering. Mayberry’s blog pre-announces that they will show enhancement-mode device results using these materials at IEDM this December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.”


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070824: Intel finds signs of heterogeneous life after silicon

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Blogger Raouf said...

Why the In2O3 compound are not used in the new heteregeneous devices ?
Raouf Bennaceur

Wed Aug 29, 02:19:00 AM PDT  
Blogger Raouf said...

Why the In2O3 componds are not used in the new intel device

Wed Aug 29, 02:22:00 AM PDT  

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.