Ed’s Threads 071026
Musings by Ed Korczynski on 26 October 2007

Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when volumes for SOI wafers have publicly stalled. However, strong technical advantages should result in new demand for engineered substrates, and CEO André-Jacques Auberton-Hervé is now leading an industry consortium to catalyze chip-makers’ adoption of SOI.

The “chateau” built to house Soitec has the classic design element of a bridge over a moat, while the mirrored sides of the building reflect the awesome beauty of the French Alps. Inside the complex is the Class1 ballroom layout of Bernin1, the company’s first fab that is now capable of producing 800K/year on ≤200mm wafers. Connected by a walkway, Bernin2 is the company’s Class10-100 ballroom layout 300mm dedicated line (also 800K/year). An overhead transport was added two years ago to increase output to handle the increased demand for all the latest-generation game consoles and AMD’s microprocessor ramp in Dresden. Though PS3 sales have been weak, Xbox and Wii game platform sales have been strong, and all use SOI chips.

Both Bernin1 and Bernin2, as well as the new 300mm line announced for Singapore, use completely standard industry tools from established OEMs to do the specialty implants and thermal treatments needed for their layer transfer process. Among the setup are TEL furnaces, Applied Materials implanters, EVG bonders (a bit customized at 300mm, instead of the standard 200mm size used in MEMS fabs), Mattson and Applied Materials RTP, and KLA-Tencor metrology tools. Over 1000 Soitec employees are running these lines 24/7 and essentially 365 day/year.

Bernin3, a stone’s throw from Bernin2, was built originally by MEMSCAP as its own fab. Essentially just a shell when it was acquired by Soitec in mid-2006, it now has three 500 m2 cleanrooms doing R&D on III-V materials such as Nanosmart GaN development, and complex pattern transfers. Transferring already patterned layers (not blanket layers) was work originally started at LETI, spun out as TraciT Technologies and then acquired by Soitec; the first product was imagers using backside illumination. Bernin3 runs 100mm, 125mm, and 150mm wafers, so the R&D tool set is flexible to handle any of these wafer sizes. If any device captures serious demand, then pilot production could occur with dedicated tools in the (currently empty) fourth space in the fab shell. Including its PicoGiga division's work on MBE epitaxy for GaN, Soitec has a lot of IP and know-how to bring to the development of high-efficiency and high-brightness LED production.

Soitec keeps only a handful of finished goods inventory on site, since the company is completely integrated into a just-in-time integrated supply-chain. Soitec maintains at least one month’s of inventory at each customer site, maintaining ownership until each wafer enters the IC fab line. Likewise, three suppliers maintain starting wafer inventory at Soitec, only “delivering” the wafers when they enter the SOI production line.

Auberton-Hervé, Soitec CEO and newly elected chairman of the SOI Industry Consortium, is modest about Soitec’s role in bringing the possibility of cost-effective SOI manufacturing to the semiconductor industry over the last decade. “We were a bit of the catalyst, but the demand was from the ecosystem,” he claims. The consortium in current form did grow out of periodic SOI user workshops Soitec had sponsored, and Auberton-Hervé notes that interactions between device researchers during a September 2006 workshop led to the demand for the creation of an open ecosystem.

To be sure, the proprietary IBM-ecosystem has had SOI design-flows, design IP, and appropriately tuned manufacturing processes for lease for many years. Yet not every company has been willing or able to work with the folks in East Fishkill, NY, and so this new consortium may really open up a new avenue to add value for many companies.

“The value of the consortium is in the ability to accelerate innovation,” said Auberton-Hervé. “We have to be more efficient in how we bring value to the whole food-chain. Roadmaps for cost in each segment will help, but it’s more global than that.” Most people think that finFETs really call for SOI, and both represent huge power-savings for portable battery-powered applications. From first-principles it seems that SOI has advantages for mixed-signal isolation. Embedded memory using ZRAM structures (license to Innovative Silicon) is also an attractive option.

With Auberton-Hervé committed to “doing well by doing good” in leading this consortium for the industry as well as for his company and shareholders, much more of the industry may end up using SOI. It may help with functional integration at 45nm and beyond, and that may help double battery life for next-generation iPods and e-Phones. SOI and other layer-transfer technologies will almost certainly become increasingly useful as simple x-y scaling inevitably slows, and Mauberger will be coordinating the operations of global Soitec fabs to keep the wafers flowing around the world.

—E.K

Labels: consortium, IC, semiconductor, SOI, wafer

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071026: Soitec catalyzes SOI consortium

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Ed’s Threads 070928
Musings by Ed Korczynski on September 28, 2007

Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).

Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.

Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.

TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.

These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.

Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.

Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”

Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”

All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.

While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.

--E.K.

Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via

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070928: Who needs through-silicon vias?

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Ed’s Threads 070921
Musings by Ed Korczynski on September 21, 2007

Flash and DRAM rule future of IC memory
A one-day technical symposium on “New Frontiers in Memory”, sponsored by the IEEE and Applied Materials, was held Sept. 20th at the Hotel Valencia in San Jose, CA. Amidst the ostentatious splendor of the flashy hotel, a standing-room-only crowd of technologists learned about the leading-edge of manufacturing the densest, fastest, cheapest IC memories. The takeaway theme: The two trains of DRAM and flash memory technologies have long “left the station” and unless and until they stop, other technologies such as phase-change RAM (PRAM) and magneto-resistance RAM (MRAM) will be relegated to niche applications.

Sung-Joo Hong, VP of R&D for Hynix, discussed the scaling limits of trench-DRAM technology determined by the control of subtle topography variations inside storage-node trenches. Retention time of the recess cell transistor will be challenged again with the introduction of 1.2V devices. With inherently smaller storage area and higher fields at junctions, extending current device architectures would result in excessively low retention time. The lowest equivalent oxide thickness (EOT) of 3Å in a 50:1 aspect ratio trench is not sufficient for 3Xnm node technology. Selective epitaxy and/or finFET (with p+ poly gates) are possible solutions, though DIBL is an inherent challenge for finFETs.

George Samachisa, VP of technology at SanDisk, showed that as flash capacity has improved while cost has dropped, it has come to overlap with hard disk drives (HDD) and DRAM/SRAM. With another 10x reduction in price, SanDisk projects that flash cost/bit could actually be less than DRAM. NAND flash costs ~$10/GB today, with ~$1.0/GB likely in 5-7 years time, and today's capacity of 16Gb/chip is expected to increase to 128-256Gb chips in 5-7 years. To continue scaling, the NAND and controller must work together for defect management, wear-out leveling, cell-cell interference mitigation, file/bad-block management, standard I/O, and DSP error-correction control to enable >2 bits/cell.

SanDisk has pushed five generations of technology in just as many years of production. In 2004 most production was 130nm, while by the end of this year the majority will be 70nm, and 2008 will be mostly 56nm with some 43nm in volume. Alternative NAND technologies (SONOS and TONOS) have so far not lived up to expectations, so SanDisk believes that floating gate is still the best candidate for scaling down to the 20nm technology node. Adding SONOS would allow NAND to be scaled one more node to 1Xnm, with 3D technology the likely successor.

Prof. H.S. Wong of Stanford U., formerly with IBM's T.J. Watson R&D center, discussed the bleeding-edge of “emerging memories” including change-storage, phase-change, nano-filament formation, ferroelectrics, magneto-resistance, stiction force, and mechanical deformation. Wong cautioned that any researcher observing hysteresis in physical phenomenon is tempted to claim a "new memory technology" -- but density, scalability, and manufacturing cost constraints tend to eliminate most from serious consideration.

Tom Andre, Freescale Semiconductor's head of toggle MRAM technology, explained that 0.18µm MRAM technology provides data retention of >20 years and unlimited endurance at 125°C for a 4Mb toggle MRAM running on 3.3V power supply and 26mm2 chip size (based on a 1.26µm2 cell size). The market space for fast and non-volatile memory allows for a price of US$4/Mb. Spin-torque MRAM, as opposed to the toggle variant, allows for more efficient writing based on current-density instead of energy transferred through a field. Distributions of write-currents can be a problem, particularly for the high-end where excessive currents can induce breakdowns.

PRAM seems promising, and the fact that ex-Intel-Flash-leader and CTO Stefan Lai has joined Ovonyx is encouraging, but this technology has been pushed for nearly 40 years by Energy Conversion Devices, Ovonyx's parent company. (This time for sure…) Samsung’s 512Mb PRAM in 90nm technology uses PN diodes, complex top contacts, and other unique processes on top of standard CMOS. Intel plans for PRAM production, too.

Metal-oxide memories have been shown with NiO, TiO, Nb2O5, Al2O5, Ta2O5, and Cr-doped perovskites. The exact mechanism is not clear, but some manner of conductive filament formation seems to be involved. Consequently, the on-current should be area-independent while the off-current should be area-dependent. Solid electrolytes such as Cu-WO3 and Cu-Cu2S could be used in the future, and theoretically scaled down to a single-atom between electrodes. HP’s crossbar nano-array architecture might fit into this categorization, too.

Any new memory technology must meet a market need, and must compete with DRAM and flash in terms of cost and functionality. “There’s a lot of room to scale DRAM before we need new memory technology,” said Applied Materials Fellow Reza Arghavani, in an exclusive interview with WaferNEWS. Arghavani points out that equipment companies can bring to memory manufacturing innovations that have been in use in logic fabs for generations, such as copper interconnects, epi-layers, HK+MG, and low-k dielectrics. “They have to be re-optimized and re-integrated, but fundamentally they are the same technologies,” he said. Charge-trap memories are just like HK+MG stacks, in the need for work-function engineering of the materials interfaces, he pointed out. “The physics of it is identical.”

For at least the last few nodes, logic has driven thin-films and new materials development, while memory has driven lithography development. “Flash is driving litho resolution, while overlay is currently being driven by DRAM,” clarified Rudi Hendel, Applied Materials' managing director, technology programs, in an exclusive interview with WaferNEWS.

Humans like to sort and store information, and the ever-greater ability to store data in digital form continues to spur demand for IC memory. SanDisk presented recent data (May 2007) from Gartner Dataquest that forecasted NAND bit demand will increase 40x from 2006 to 2011, with major demand for PC, mobile phones, USB, and media players. In the last ten years, flash has already replaced a host of older storage mediums (35mm film, floppy/Zip/Clik/tape drives) and is well on the way to replacing CDs and ultra-small HDD (<1.3”). The message is clear -- other promising memory technologies have a tough train to catch.

–E.K.

PS
A comment (below) that this blog entry does not distinguish between stand-alone and embedded applications is certainly correct; stand-alone memory IC technology can be more easily compared in terms of cost/density/performance, while embedded applications must consider additional cost and performance increases. Such analysis is a bit beyond the scope of what can be covered in a relatively short blog entry.

Labels: DRAM, flash, future, IC, memory, MRAM, PRAM

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070921: Flash and DRAM rule future of IC memory

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Ed’s Threads 070824
Musings by Ed Korczynski on August 24, 2007

Intel finds signs of heterogeneous life after silicon
With CMOS circuits using silicon channels running into performance limitations, doping with germanium and straining the lattice have already been used to push the limits. The limits of silicon remain, though, and so compound semiconductors are again under consideration as building blocks for mainstream ICs—this time integrated on top of 300mm silicon wafers.

The first solid-state transistors were built with germanium (Ge), but Ge crystals do not grow a nice surface-passivating oxide as do silicon crystals, and the oxide is vital to prevent surface defects that would otherwise kill performance. Grown silicon oxide has been the heart of cost-effective high-volume IC production for over 40 years. Even high-k (HK) gate dielectrics based on hafnium-oxides will typically be used on top of a grown and partially etched-back silicon oxide layer.

What comes after high-k and metal-gates (HK+MG)? Heterogeneous integration of compound semiconductors will completely replace the silicon channel. Silicon wafers would still be used, but only as physical supports for different NMOS and PMOS transistor materials. The new channel materials will be deposited and/or grown using technologies such as metal-organic CVD (MOCVD), solid-phase epitaxy (SPE), and spike/flash anneals.

Though HK+MG has been spun as the biggest change in 40 years, when compound semiconductors are integrated with silicon it will be a far greater integration challenge for it will require an even greater number of new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.

This summer, Intel researchers achieved success at fabricating high performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. On their internal blog, they show curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.

Mike Mayberry, Intel’s director of components research, has articulated five general areas of research and develop needed to create a competitive commercial heterogeneous semiconductor fab technology:
1) put compound semiconductors on silicon wafers,
2) find different high-k dielectrics for the gates,
3) develop PMOS materials to go with known NMOS,
4) develop enhancement-mode devices instead of depletion-mode, and
5) “Make them small enough to compete with silicon transistor densities.”

The last is the tricky part. These circuits are conceived of as being possible at or past the 22nm node, so that means high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.

By the time InSb and InGaAs could be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. In an email exchange with me after his initial blog posting, Mayberry answered some questions relating to finFETs as possible structures for heterogeneous integration. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate and thus, that builds pressure to find a vertical solution for III-V,” he confirmed, but he admitted that, “we do not as yet have a solution to that problem.”

If finFETs are used, new metal alloys will need to be developed to be able to form minimal resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.

In my email exchange with Mayberry, he confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows—and will let us know—is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.

This is all starting to get into some serious materials engineering. Mayberry’s blog pre-announces that they will show enhancement-mode device results using these materials at IEDM this December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.”

–E.K.

Labels: compound semiconductor, heterogeneous, IC, integration, Intel

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070824: Intel finds signs of heterogeneous life after silicon

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Ed’s Threads 070727
Musings by Ed Korczynski on July 27, 2007

Working together to reach nirvana
SEMICON West hasn’t been a “selling show” (i.e., a tradeshow where you actually sell stuff) for well over a decade, so why do people still bother to attend it? There are still endless meetings and seminars and panel discussions that provide vital connections and information to keep the industry going. Manufacturing ICs with minimal dimensions below 45nm creates technical challenges that combine with consumer-market challenges to create extreme rewards for success and extremely expensive penalties for failure. For any IC fab company to succeed in the future, partners will be needed and new ways of working together will have to become new habits, as detailed in two separate panel discussions held on succeeding days by Praxair Electronics and DuPont Electronic Materials.

The first few decades of the semiconductor industry were based on vertical business integration like that championed by Henry Ford at the carmaker's Rouge Plant, where controlling the stream of raw materials and custom-built equipment resulted in massive economies of scale. Vertical organization under a strong top customer leads to a clear hierarchy of power, and corresponding norms of one-way information flow, dual-source strategies for all suppliers, and limited motivation for fixed relationships.

By the 1990s, however, the global semiconductor industry had became vertically dis-integrated, with separate levels for original equipment manufacturers (OEM) and specialized subsystems manufacturers — yet the mindset of vertical integration typically remained.

Today, we’re in an era where the complexity of manufacturing has increased to the point that even the biggest integrated device manufacturers (IDM) like Intel and IBM and TI have to partner to develop technology. With consortia and joint-development projects (JDP) now driving the creation of most new intellectual property (IP) in the industry, and with the increased costs and risks of nanometer-era IC fabrication, we must develop new habits of working together and sharing information.

Carrying the theme that “In sharing knowledge we can achieve true enlightenment,” Praxair’s July 17th event at SEMICON West featured keynotes by SEMATECH’s Raj Jammy and processing expert John Borland, discussing the technical challenges of 32nm node transistor fabrication. In the panel discussion that followed (which I had the pleasure of moderating), I attempted to express some “Zen-like” ideas about working together in a harmonious ecosystem. More details from the Praxair panel can be found in SST On the Scene video interviews available online.

Meanwhile, DuPont’s July 18th seminar entitled "Technology Partnerships and Tools for the Future" featured presentations by executives from IDMs, OEMs, academia, and a consortium (SEMATECH's Raj Jammy again) on how cooperation is needed to meet the increasingly demanding requirements of advanced ICs.

Mansour Moinpour, materials technology and engineering manager for Intel’s global fab materials organization, showed that even the largest company in the industry with potentially the greatest internal resources has used an ever increasing number of partners over the last decade. Large companies today have typically systematized interactions with universities and other research organizations. “I think the challenge is going to be how to make sure that we facilitate the interaction of the small companies with the universities,” explained Farhang Shadman, Regents Professor of Chemical and Environmental Engineering at the U. of Arizona, and director of its Center for Environmentally Benign Semiconductor Manufacturing. “I think this is very important, because they are in greatest need of research facilities.”

Basic human trust is essential to making deals that can quickly bear fruit, combined with prior aggregate experience, and some manner of mutual benefit on a strategic level. Jammy said that templates and standards have allowed SEMATECH to reduce the time needed to get a signed contract from one-half year down to weeks. John Behnke, VP of process development and transfer for Spansion, commented, “There are some pretty good templates that the legal community and the different corporations begin with, which helps the process. I think it has matured in the last maybe two to three years. So that helps.”

Behnke reminds us that trust is still vital to efficient business, and trust that your ideas will not be stolen is perhaps the most vital. “Let's say that the room is dark and the solution to that is to invent the lightbulb,” he explained. Once the hard work of creating a working lightbulb is complete, “the person who said the room was dark thinks that it's all theirs.” This sort of mindset was not uncommon in the past. Fortunately, it seems that most of us now realize that an attitude of “enlightened altruism”—in which we all work for mutual benefit—really does result in the greatest individual benefit too.

–E.K.

Labels: ecosystem, fab, IC, partner, semiconductor

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070727: Working together to reach nirvana

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Ed’s Threads 070713
Musings by Ed Korczynski on July 13, 2007

High-k, low-k, special-k, super-k
SEMATECH has announced that the R&D; organization has developed a “super High-k” dielectric for ICs. How “super” can it be at 30-40 k (double the 15-20 k of hafnium oxide)? How easy might it be to integrate? We can’t guess since the material and its properties beyond the dielectric constant remain secret. All we know is that some people want us to call it “super-k” or “SHK”, and I’m against this as title inflation.

As the semiconductor manufacturing industry pushes the limits of CMOS architectures to ever smaller physical dimensions—45nm node production now ramping—materials properties must improve to ensure proper IC function. New materials are used throughout the chip, yet some of the basic terms used to describe these new materials were never standardized. In particular, the dielectric constant (k)—the measure of a material’s polarizability by a passing electromagnetic wave—was formerly kept in a tight range by using only silicon oxide (k~4) and silicon nitride (k~7) films. With 4-7 established as the “medium” range of k by default, anything <4>7 counts as “High-k” (HK). Note that industry convention capitalizes “High” while not capitalizing “low” in these terminologies. Also note that "k" is properly itallicized but does not always appears as such.

Now 45nm node chips will employ materials with k values ranging from 2.5 to 20, and even lower and higher k materials are under development. Relatively higher k is desired in transistor gates to ensure minimal current leakage when biasing the gate to open the channel, while relatively lower k is desired in intermetal dielectrics (IMD) to ensure minimal coupling and delay to propagating signal pulses.

As the industry has developed low-k dielectrics for IMD, and High-k dielectrics for gates (as well as for memory storage), terminology has been confusing.

Looking first at low-k, the industry first used fluorinated silicon-oxide glass (FSG) with k~3.5, then silicon oxycarbide (SiOC) and silicon-carbon oxyhydride (SiCOH, often pronounced “psycho”) films with k~3.0 for IMD. Since air or vacuum has k of 1, adding pores or gaps to SiCOH as a fraction of the volume proportionally decreases k for the final film. Porous low-k (PKL) films may also be termed ultra low-k (ULK) or extreme low-k (ELK), regardless of where they fall in the 2.0-2.7 range.

Polyimide, benzo-cyclo-butene (BCB), and parylene are all 2.5-3.0 k range films used in passivation and packaging, though they are not commonly termed ULK or ELK. So, for a given chip, it’s possible that a porous SiCOH film of k=2.6 would be termed ULK, while the k=2.6 BCB film used on the same chip is merely “low-k”.

Terminology moving in the other direction was formerly simpler. Starting with k ~7 for silicon nitride as the top end of the “medium” k range, the industry currently uses aluminum oxide and hafnium oxide as HK films in the 8-10 and 15-20 ranges, respectively. Less publicized in recent years but used in volume production nonetheless, ferroelectric RAM (FRAM) fabs use lead-zirconium-titanate (PZT) and barium-strontium-titanate (BST) materials with k values in the 100-300 range. For years, any dielectric with k>7 was simply termed “High.”

Now that SEMATECH wants to call 30-40 the “super” dielectric constant range, what are we to call k>50? Shall we follow the hard-disk drive (HDD) industry terminology for magneto-resistive heads and call PZT films “giant-high-k” and BST films “colossal-high-k” starting now? What about the poor FRAM marketeers who suffered without having these terms to describe their products for so many years—who could they sue for lost brand-value? Why not retroactively inflate terminology for other materials and call graded-SiON and ONO-stacks “special-k?”

In all seriousness, we should employ moderation in terminology, and just call this new material another high-k (HK). In the name of simplification, that to me would indeed be "super."

—E.K.

Labels: dielectric, high-k, IC, interconnect, low-k, metal gate, terms

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070713: High-k, low-k, special-k, super-k

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Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman, et.al, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

Labels: airgap, fab, IBM, IC, Intel, interconnect, low-k, self-assembly, ULK

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070525: Intel-IBM fab hype-war and truths

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Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

Labels: airgap, fab, IBM, IC, interconnect, low-k, self-assebly, ULK

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070504: IBM add airgaps for faster chips

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Ed’s Threads 070427
Musings by Ed Korczynski on April 27, 2007

Planning for life after CMOS commoditization...today
It’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s.

Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors.

In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP).

Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon.

Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all.

With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan.

IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs.

Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day.

— E.K.

Labels: business, CMOS, commodity, fab, IC, strategy

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070427: Life after CMOS commoditization

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