071211: HK+MG real details shown at IEDM
Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007
It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitusu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).
Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound -- no additional details yet on other elements likely to be used in this ALD step, whether the phase of the final material is amorphous or crystalline, or what is the specific interface from the HK to the highly-strained channel. (In a side conversation after Mistry's talk, Intel Fellow Tahir Ghani confirmed the need for this interface, but would provide no details, only noting that it is critical for mobility.) pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/μm IOFF and at 160nm contacted gate pitch. pMOS drive current of 1.07 mA/μm (51% improvement over 65nm), while nMOS drive current is 1.36mA/μm (12% better than 65nm). SRAM arrays with cell sizes of 0.346μm2 and 0.383μm2 (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields.
Figure. TEM micrograph of 45nm Intel high-k + metal gate pMOS transistor. (Source: IEDM2007 10.2)
Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:
- STI, well, and VT implants,
- ALD (18-20Å) of HK gate dielectric,
- Polysilicon deposition and gate patterning,
- Source/drain extensions, spacer, Si recess and SiGe deposition,
- Source/drain anneal, Ni salicidation, ILD0 deposition,
- Poly opening CMP, poly removal,
- pMOS work-function metal deposition,
- Metal gate patterning, nMOS work-function metal deposition, and
- Metal gate Al fill and Al CMP, etch-stop layer deposition.
IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low VT CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low VT values of ±0.25V and unstrained IDSAT of 1035/500μmA/μm (for nMOS/pMOS respectively) at IOFF=100nA/μm and VDD=1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La2O3) for nMOS and aluminum oxide (Al2O3) for pMOS to lower EOT from ~17 to ~15 while maintaining the same target VT. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La2O3 thickness control allows for VT turning from 0.2 to 0.6 for nMOS. HfSiO shows lower VT and higher mobilities compared to HfSiON. The laser-only anneal further results in improved LG scaling of 15nm and a 2Å TINV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.
Prof. A. Toriumi et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials Science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO2 has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La2O3 increases the crystallization temperature up to 800-1000°C (over the range of 20%-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher-k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO2 and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.
Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a “Flexible, simplified CMOS using HK+MG on Si(110). “What we have shown is that if we add capping layers on top of the dielectric we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard (100) to (110) orientation allows for mobility increase of 3X for holes, while electron mobility drop by ~1/2. Mixed orientation -- Si(100) for nMOS, and Si(11) for pMOS -- has been examined but process complexity, cost, and variability seem unattractive. Data for Si(110) planar CMOS is relatively similar to multiple orientation approach (with much lower manufacturing cost), though an pre-amorphosizing implant is used to minimize diffusion which is faster in (110) compared to (100) silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25μm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of (110) or (100). Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for (110), using (110) lowered GIDL by an order of magnitude compared to (100).
CEA-LETI-MINATEC/Soitec use TiN metal over HfO2 HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi et al. (IEDM '97) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10μm were fabricated, all with widths of 10μm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (IOn=780&MU;MA/μm) and LP (IOFF=10pA/μm) devices.
Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO4) alloy gate dielectric and hafnium dioxide (HfO2) films were formed by atomic layer deposition using metal halides and heavy water as precursors.
Labels: ALD, future, high-k, HK+MG, IBM, Intel, metal gate, transistor
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071211: HK+MG real details shown at IEDM
070921: Flash and DRAM rule future of IC memory
Ed’s Threads 070921Musings by Ed Korczynski on September 21, 2007
Flash and DRAM rule future of IC memory
A one-day technical symposium on “New Frontiers in Memory”
, sponsored by the IEEE and Applied Materials, was held Sept. 20th at the Hotel Valencia in San Jose, CA. Amidst the ostentatious splendor of the flashy hotel, a standing-room-only crowd of technologists learned about the leading-edge of manufacturing the densest, fastest, cheapest IC memories. The takeaway theme: The two trains of DRAM and flash memory technologies have long “left the station” and unless and until they stop, other technologies such as phase-change RAM (PRAM) and magneto-resistance RAM (MRAM) will be relegated to niche applications.
Sung-Joo Hong, VP of R&D for Hynix, discussed the scaling limits of trench-DRAM technology determined by the control of subtle topography variations inside storage-node trenches. Retention time of the recess cell transistor will be challenged again with the introduction of 1.2V devices. With inherently smaller storage area and higher fields at junctions, extending current device architectures would result in excessively low retention time. The lowest equivalent oxide thickness (EOT) of 3Å in a 50:1 aspect ratio trench is not sufficient for 3Xnm node technology. Selective epitaxy and/or finFET (with p+ poly gates) are possible solutions, though DIBL is an inherent challenge for finFETs.
George Samachisa, VP of technology at SanDisk, showed that as flash capacity has improved while cost has dropped, it has come to overlap with hard disk drives (HDD) and DRAM/SRAM. With another 10x reduction in price, SanDisk projects that flash cost/bit could actually be less than DRAM. NAND flash costs ~$10/GB today, with ~$1.0/GB likely in 5-7 years time, and today's capacity of 16Gb/chip is expected to increase to 128-256Gb chips in 5-7 years. To continue scaling, the NAND and controller must work together for defect management, wear-out leveling, cell-cell interference mitigation, file/bad-block management, standard I/O, and DSP error-correction control to enable >2 bits/cell.
SanDisk has pushed five generations of technology in just as many years of production. In 2004 most production was 130nm, while by the end of this year the majority will be 70nm, and 2008 will be mostly 56nm with some 43nm in volume. Alternative NAND technologies (SONOS and TONOS) have so far not lived up to expectations, so SanDisk believes that floating gate is still the best candidate for scaling down to the 20nm technology node. Adding SONOS would allow NAND to be scaled one more node to 1Xnm, with 3D technology the likely successor.
Prof. H.S. Wong of Stanford U., formerly with IBM's T.J. Watson R&D center, discussed the bleeding-edge of “emerging memories” including change-storage, phase-change, nano-filament formation, ferroelectrics, magneto-resistance, stiction force, and mechanical deformation. Wong cautioned that any researcher observing hysteresis in physical phenomenon is tempted to claim a "new memory technology" -- but density, scalability, and manufacturing cost constraints tend to eliminate most from serious consideration.
Tom Andre, Freescale Semiconductor's head of toggle MRAM technology, explained that 0.18µm MRAM technology provides data retention of >20 years and unlimited endurance at 125°C for a 4Mb toggle MRAM running on 3.3V power supply and 26mm2 chip size (based on a 1.26µm2 cell size). The market space for fast and non-volatile memory allows for a price of US$4/Mb. Spin-torque MRAM, as opposed to the toggle variant, allows for more efficient writing based on current-density instead of energy transferred through a field. Distributions of write-currents can be a problem, particularly for the high-end where excessive currents can induce breakdowns.
PRAM seems promising, and the fact that ex-Intel-Flash-leader and CTO Stefan Lai has joined Ovonyx is encouraging, but this technology has been pushed for nearly 40 years
by Energy Conversion Devices, Ovonyx's parent company. (This time for sure…) Samsung’s 512Mb PRAM in 90nm technology uses PN diodes, complex top contacts, and other unique processes on top of standard CMOS. Intel plans for PRAM production, too.
Metal-oxide memories have been shown with NiO, TiO, Nb2O5, Al2O5, Ta2O5, and Cr-doped perovskites. The exact mechanism is not clear, but some manner of conductive filament formation seems to be involved. Consequently, the on-current should be area-independent while the off-current should be area-dependent. Solid electrolytes such as Cu-WO3 and Cu-Cu2S could be used in the future, and theoretically scaled down to a single-atom between electrodes. HP’s crossbar nano-array architecture
might fit into this categorization, too.
Any new memory technology must meet a market need, and must compete with DRAM and flash in terms of cost and functionality. “There’s a lot of room to scale DRAM before we need new memory technology,” said Applied Materials Fellow Reza Arghavani, in an exclusive interview with WaferNEWS. Arghavani points out that equipment companies can bring to memory manufacturing innovations that have been in use in logic fabs for generations, such as copper interconnects, epi-layers, HK+MG, and low-k dielectrics. “They have to be re-optimized and re-integrated, but fundamentally they are the same technologies,” he said. Charge-trap memories are just like HK+MG stacks, in the need for work-function engineering of the materials interfaces, he pointed out. “The physics of it is identical.”
For at least the last few nodes, logic has driven thin-films and new materials development, while memory has driven lithography development. “Flash is driving litho resolution, while overlay is currently being driven by DRAM,” clarified Rudi Hendel, Applied Materials' managing director, technology programs, in an exclusive interview with WaferNEWS.
Humans like to sort and store information, and the ever-greater ability to store data in digital form continues to spur demand for IC memory. SanDisk presented recent data (May 2007) from Gartner Dataquest that forecasted NAND bit demand will increase 40x from 2006 to 2011, with major demand for PC, mobile phones, USB, and media players. In the last ten years, flash has already replaced a host of older storage mediums (35mm film, floppy/Zip/Clik/tape drives) and is well on the way to replacing CDs and ultra-small HDD (<1.3”). The message is clear -- other promising memory technologies have a tough train to catch.
A comment (below) that this blog entry does not distinguish between stand-alone and embedded applications is certainly correct; stand-alone memory IC technology can be more easily compared in terms of cost/density/performance, while embedded applications must consider additional cost and performance increases. Such analysis is a bit beyond the scope of what can be covered in a relatively short blog entry.
Labels: DRAM, flash, future, IC, memory, MRAM, PRAM
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070921: Flash and DRAM rule future of IC memory
Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.