Ed’s Threads 071026Musings by Ed Korczynski on 26 October 2007
Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec
COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when volumes for SOI wafers have publicly stalled. However, strong technical advantages should result in new demand for engineered substrates, and CEO André-Jacques Auberton-Hervé is now leading an industry consortium to catalyze chip-makers’ adoption of SOI.
The “chateau” built to house Soitec has the classic design element of a bridge over a moat, while the mirrored sides of the building reflect the awesome beauty of the French Alps. Inside the complex is the Class1 ballroom layout of Bernin1, the company’s first fab that is now capable of producing 800K/year on ≤200mm wafers. Connected by a walkway, Bernin2 is the company’s Class10-100 ballroom layout 300mm dedicated line (also 800K/year). An overhead transport was added two years ago to increase output to handle the increased demand for all the latest-generation game consoles and AMD’s microprocessor ramp in Dresden. Though PS3 sales have been weak, Xbox and Wii game platform sales have been strong, and all use SOI chips.
Both Bernin1 and Bernin2, as well as the new 300mm line announced for Singapore, use completely standard industry tools from established OEMs to do the specialty implants and thermal treatments needed for their layer transfer process. Among the setup are TEL furnaces, Applied Materials implanters, EVG bonders (a bit customized at 300mm, instead of the standard 200mm size used in MEMS fabs), Mattson and Applied Materials RTP, and KLA-Tencor metrology tools. Over 1000 Soitec employees are running these lines 24/7 and essentially 365 day/year.
Bernin3, a stone’s throw from Bernin2, was built originally by MEMSCAP as its own fab. Essentially just a shell when it was acquired by Soitec in mid-2006
, it now has three 500 m2 cleanrooms doing R&D on III-V materials such as Nanosmart GaN development, and complex pattern transfers. Transferring already patterned layers (not blanket layers) was work originally started at LETI, spun out as TraciT Technologies and then acquired by Soitec
; the first product was imagers using backside illumination. Bernin3 runs 100mm, 125mm, and 150mm wafers, so the R&D tool set is flexible to handle any of these wafer sizes. If any device captures serious demand, then pilot production could occur with dedicated tools in the (currently empty) fourth space in the fab shell. Including its PicoGiga division's work on MBE epitaxy for GaN
, Soitec has a lot of IP and know-how to bring to the development of high-efficiency and high-brightness LED production.
Soitec keeps only a handful of finished goods inventory on site, since the company is completely integrated into a just-in-time integrated supply-chain. Soitec maintains at least one month’s of inventory at each customer site, maintaining ownership until each wafer enters the IC fab line. Likewise, three suppliers maintain starting wafer inventory at Soitec, only “delivering” the wafers when they enter the SOI production line.
Auberton-Hervé, Soitec CEO and newly elected chairman of the SOI Industry Consortium, is modest about Soitec’s role in bringing the possibility of cost-effective SOI manufacturing to the semiconductor industry over the last decade. “We were a bit of the catalyst, but the demand was from the ecosystem,” he claims. The consortium in current form did grow out of periodic SOI user workshops Soitec had sponsored, and Auberton-Hervé notes that interactions between device researchers during a September 2006 workshop led to the demand for the creation of an open ecosystem.
To be sure, the proprietary IBM-ecosystem has had SOI design-flows, design IP, and appropriately tuned manufacturing processes
for lease for many years. Yet not every company has been willing or able to work with the folks in East Fishkill, NY, and so this new consortium may really open up a new avenue to add value for many companies.
“The value of the consortium is in the ability to accelerate innovation,” said Auberton-Hervé. “We have to be more efficient in how we bring value to the whole food-chain. Roadmaps for cost in each segment will help, but it’s more global than that.” Most people think that finFETs really call for SOI, and both represent huge power-savings for portable battery-powered applications. From first-principles it seems that SOI has advantages for mixed-signal isolation. Embedded memory using ZRAM structures (license to Innovative Silicon
) is also an attractive option.
With Auberton-Hervé committed to “doing well by doing good” in leading this consortium for the industry as well as for his company and shareholders, much more of the industry may end up using SOI. It may help with functional integration at 45nm and beyond, and that may help double battery life for next-generation iPods and e-Phones. SOI and other layer-transfer technologies will almost certainly become increasingly useful as simple x-y scaling inevitably slows, and Mauberger will be coordinating the operations of global Soitec fabs to keep the wafers flowing around the world.
Labels: consortium, IC, semiconductor, SOI, wafer
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071026: Soitec catalyzes SOI consortium
Ed’s Threads 070907Musings by Ed Korczynski on September 7, 2007Lam & Novellus both strip wafer edges
This is a tale of two companies, two machines, and two different ways to solve one related problem: wafers have edges. Silicon wafer edges perturb plasma flows in process chambers, and so induce inherent non-uniformities in processing. Silicon wafer edges are seemingly the main source of defects for immersion lithography. Advanced fabs today typically specify a 2mm edge exclusion for wafers, and Novellus and Lam have responded with new hardware to dry strip edges.Novellus’ downstream dry edge strip
. Depth-of-focus along with etch-rate selectivity challenges have led to the need for hardmasks in advanced IC lithography. The hardmask material must be properly chosen for selectivity to the underlying layer to be etched. In many cases, it can be an amorphous carbon PECVD thin-film that is “ashable” (a misnomer since it can be dry stripped without any ash-like residue remaining). A wide variety of hydrocarbon precursors may be used, and deposition parameters must be properly controlled to ensure the final film structure is composed of sp2 carbon-bonds for transparency and film stability. “We’re getting 20:1 selectivity, and extinction coefficient value at 633nm of 0.11,” claimed Julian Hsieh, senior director of product management for the dielectrics business group at Novellus Systems.
To eliminate any edge particles that could kill dice, the Vector Express PECVD tool from Novellus
now provides a new dry edge-bead removal (EBR) capability into the outgoing loadlock (which SST recently reviewed
). Using an off-the-shelf downstream plasma generator to crack O2 into mono-atomic oxygen (Fig.1), amorphous carbon (red in the figure) is stripped off the wafer edge while the top-surface is masked by center shield hardware.
Field-retrofittable to the Vector platform, the EBR has additional potential applications. Since mono-atomic oxygen is extremely reactive, it may be able to clean other PECVD films off of the edge/bevel of wafers. ”If you have this capability you may be able to use it to solve other problems,” admitted Hsieh.
In addition to clean wafer edges, it’s essential that deposited film properties remain constant all the way to the 2mm edge exclusion. Ensuring a uniform deposition environment across the wafer—in terms of temperature, plasma energy parameters, and precursor flows—requires careful optimization of chamber hardware. Consequently, Novellus modified the Vector Express chamber hardware to include new plasma confinement shields.Lam’s plasma ring edge strip
. Also using a physical shield, Lam Research Corp. now sells a plasma edge clean module that can be part of a cluster on the company’s 2300 hardware platform
. A capacitively coupled plasma is shielded from the wafer topside by a shield precision engineered to float fractions of a millimeter above the wafer surface (a gap too small to be seen in Fig.2). No electrostatic chuck is used to minimize cost.
“If we as an industry had recognized the value of bevel clean, we would have done it earlier,” said Rick Gottscho, group VP and GM of Lam's etch business, noting that this market opening started with Korean memory customers. Yield improvements of 1%-4% are possible using rigorous dry edge strip, he said, adding that a 3-4 chamber cluster of these edge strippers may see production.
Lam quietly released this tool in 1Q07, and now claims to be engaged with 18 of the top 25 capital spenders. “Most of our customers today are in evaluation phases, looking at the yield benefits, and the applications first to use it, but the pull is very strong,” said Gottscho. He said that chamber throughputs are close to what you’d expect from a stripper dealing with low-k etch processes.
Both Novellus and Lam have released useful tools for high-volume production, and both use a hardware shield to protect wafer top-sides while stripping films from edges. However, they are inherently different in the plasma hardware. Novellus’ remote generator design is safe and simple and fits into a load-lock without taking up chamber space. Lam’s capacitively coupled plasma ring provides an additional degree of processing freedom with ion bombardment, but requires the space of a process chamber to do so.
Applications-specific hardware solutions such as these are just what the industry needs to maintain productivity while ramping the production of nanometer-node ICs. While the core technologies are not new, they have been combined in new ways based on direct feedback from end-users. The natural evolution of sophisticated hardware continues within the industry ecosystem.
Labels: edge, Lam, Novellus, plasma, silicon, strip, wafer
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070907: Lam & Novellus both strip wafer edges