Ed’s Threads 080222Musings by Ed Korczynski on February 22, 2008TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect
, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman
The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.
There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.
In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer.An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV
. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks.
Image sensors for camera modules are already in volume production, with major investments by Tessera
in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.
Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion sq.in. of silicon by the year 2010
, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV.
Labels: blind TSV, interconnect, interposer, silicon, through-silicon via
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080222: TSV forecast for millions of wafers
Ed’s Threads 070928Musings by Ed Korczynski on September 28, 2007Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California
. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).
Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.
Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.
TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias”
for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.
These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable
and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.
Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.
Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal
), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”
Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”
All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer
. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.
While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.
Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via
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070928: Who needs through-silicon vias?