Ed’s Threads 060922
Musings by Ed Korczynski on 22 September 2006

SEMInvest panel bullish on torpor
Yesterday SEMI held a SEMInvest breakfast panel in Palo Alto, and at one point the analysts seemed to be saying that we were too popular, so no one liked us anymore. Moderator Bruce Rhine—fresh off the success of selling another company (this time Accent Optical to Nanometrics)—led the panel in discussing why the biz looks good but not so great these days. Large original equipment manufacturing (OEM) companies’ stock prices are not expected to outgrow the S&P; 500.

Despite the lackluster forecast for stock prices, underlying business seems solid. Global semiconductor industry Capital Expenditures (CapEx) on specialized OEM tools should be near $47B in 2007 followed by $51B in 2008, according to Jay Deahna, Managing Director, Semiconductor Capital Equipment, JP Morgan. Deahna said that orders by logic IDMs have already peaked for this cycle, orders for memory production particularly DRAM will increase, and NAND Flash is only now slowing after 100% growth YoY in 2005. The foundry capacity utilization average low for the current cycle may be only ~85%, and such a high trough should stimulate a strong next growth period.

The semiconductor industry has always dealt with cyclical demand, but the time-scales have shrunk significantly over the decades. The first big customers for ICs were governments, particularly military departments, and cycles occurred every ten years with new contract wins. The next big customers for ICs were corporations, and cycles occurred every five years in sync with CapEx depreciation.

Now everyone agrees that individual consumers are the big customers, and demand cycles occur every year or two based on planned-obsolescence, fickle whims, and global macro-economics. Robert Maire, Semiconductor Capital Equipment, Needham & Co. observes that consumers driving demand means that in addition to supply:demand balancing we must now also consider seasonal demand patterns. For example, a large portion of consumer electronics spending occurs in the month of December.

Avinash Kant, VP Equity Research, Advanced Semiconductor, Canaccord Adams, was long-term bullish on the CapEx market, due to OEM buy cycles becoming shorter and less severe, and an expected steady unit demand for ICs. Gary Hsueh, Sr. Analyst, Semiconductor Capital Equipment, CIBC World Markets, tried to make bear noises in a talk called “Don’t Rush to Call a Shallow Bottom” and noted that OEM stocks in 2006 have underperformed the S&P; 500 by 6%, though he does expect a 20% global CapEx increase next year. Maire stated that the cyclical volatility remains inherent to our industry, which accounts for our discounts versus the S&P 500.

The industry has matured so that it no longer fits into a “growth” category for investors. Deahna said stocks don’t really move upward unless hedge-funds and other funds make sizable investments. Maire said hedge funds are much less interested in this space. “What’s the point of investing in AMAT at 17 when the one year target is only 21?” Torpid growth in stock prices is why no one is very upbeat.

Larger broad-line companies are expected to merely perform to the industry, so smaller single-line companies appear relatively more attractive. Deahna believe that when Intel’s 45nm CapEx pie is cut, larger slices will go to ASML, Lam, and Varian. Yield management and metrology companies will generally do well since manufacturing just keeps getting more complex. We must all hope that Microsoft’s next bloatware is finally released sometime in 2007 so that it can inevitably suck up vast quantities of DRAM, but meanwhile our inner Extreme Elmo is dancing to our clip-on iPod.

—E.K.
posted by [email protected]
060922: SEMInvest Panel Bullish on Torpor

Post a Comment

Ed’s Threads 060915
Musings by Ed Korczynski on 15 September 2006

Middle-life Crisis for the HDD; Can’t Afford a Flashy Sports Car
September 13, 2006 was the 50th birthday of the hard-disk drive (HDD), and hundreds of people gathered to acknowledge RAMAC’s birthday with a panel of luminaries at the Diskcon tradeshow in Santa Clara, California. Floppies and tapes have come and gone, and the HDD is still the champion of magnetic storage with theoretical room to increase density by yet another factor of 100 over current records. Flash chips may take away much of the <1” form-factor market, but chips need backup so HDD demand is expected to only increase. Despite all of this, HDDs are commodity products with very thin profit margins.

One of the birthday celebration anecdotes shared by Hitachi Global Storage Technologies, the current custodian of all that began humbly in a rented lab space at 99 Autumn Street in downtown San Jose, included details that RAMAC’s first magnetic recording media were iron-oxide bits. Rust particles in solution strained through a pair of nylon stockings for size control prior to spin casting upon the disk was part of the first manufacturing process for RAMAC. It worked…though head-crashes due to stray particles were not uncommon.

Ever since RAMAC, it’s been longitudinal recording with bits stored length-wise, but we are finally getting close to the minimum bit size. If we try to magnetize smaller magnetic domains they just don’t “hold” in a single-layer. However, we can add another layer to the disk media, and then use perpendicular recording between layers to store even smaller bits. Perpendicular recording technology was used with magnetic drums over 100 years ago, and 50 years after it was first considered for disks, it is now in use.

The Magnetic Disk History Center maintains wonderful archives such as Al Hoagland’s 2002 IEEE Transactions on Mangetics paper, which recounts the early years (1955-1960) of developing the modern flying recording head and informs us that the initial prototypes used perpendicular recording. Censtor did some work with perpendicular in the late 1980s to mid-1990s, but it just wasn’t needed then. The HDD biz has been running on thin profit margins for decades; play it safe, keep the same manufacturing methods, you can’t afford the flashy sports car.

Giant- and Colossal-Magneto Resistance thin film heads extended relatively simple coil designs, which combined with reduced flying heights over smoother media surfaces to push the limits of longitudinal recording. Now perpendicular multi-layer media with 100Gb/in2 density is shipping today, 300Gb/in2 have been shown in R&D;, and 500Gb/in2 seems to be the current limit. Recording at 230Gb/in2 density which would enable a one terabyte 3.5-inch drive, according to Hitachi.

Shrinking domains beyond perpendicular requires revolutions in both the media and the head: discretely engineered ~20nm grains for media, and thermally assisted writing using a nano-scale laser integrated inside the write-head. Thermally-Assisted Recording (TAR) of patterned media should allow 100-Terabyte drives in 10 years. Serious investments in nanotechnology R&D; and sophisticated manufacturing equipment will be needed.

The HDD biz has grown to a point where equipment supplier Veeco’s CEO Ed Braun observes, “An equipment supplier base is almost viable, if we don’t listen to Wall Street.” Braun showed forecasts that the HDD industry will invest ~10% of revenue in capital equipment spending, increasing from ~US$3B to ~5B over 2005-2010. This is good, but the fun sports car is probably still out of reach.

— E.K.
posted by [email protected]
060915: HDD Mid-life Crisis; Can't Afford a Flashy Sports Car

Post a Comment

Ed’s Threads 060908
Musings by Ed Korczynski on 8 September 2006

Silicon Valley’s Soul and the HP Board Scandal
A battle for corporate culture has been raging inside HP for seven years, and it starts at the top. Recently, someone on the board of directors was thought to be leaking info to newspapers. The board chair paid flunkies to spy on reporters and other board members, and some flunkies weaseled their way into personal phone records. Now the California Attorney General has determined that the spying was criminal and, “galactically stupid.” When cultures clash it can get ugly.

Culture inside of a company determines what, why, when, and how things get done, and culture starts at the top. The board of directors chooses the CEO whose personal style influences the senior executives, which influences managers, which influences workers. A dictatorial CEO creates a culture of one-way information flow (always top-down) and “doing what you are told,” which may be fine for certain manufacturing operations. In contrast, a CEO can create a culture of two-way information flow and individual creativity, which IMHO is better for high-tech engineering-focused companies.

Hewlett and Packard were not just smart technologists, they were gifted in intuiting how to structure a healthy high-tech organization that could grow to the scale of 100,000 employees. Many structures that work well at a scale of 100 employees fail at 1000, and a hierarchy to manage 1000 often breaks down if grown to 10,000. Yet HP was able to grow and prosper using what came to be known as “The HP Way.” The first company to hire me was run by ex-HP folks who brought the HP Way with them, and I learned to appreciate the culture as a very pragmatic way to motivate people to work hard and produce great products. Like many people, I consider it to essentially be the “soul” of Silicon Valley. Lew Platt, HP CEO 1992-1999, said, “Almost every one of the practices that people look at as soft or nice come down to being damn good business sense.”

When Carly Fiorina was made CEO at the peak of the “dot-com hysteria” in 1999, she was hired in part to invigorate a mature yet seemingly staid organization. She began to change the culture while remaining distant from other employees. She reportedly didn’t “manage by wandering around” (MBWA) or eat in the company cafeteria as had her predecessors. Then she forced the merger with Compaq, and it appeared to some that she was motivated mainly to do a big deal that would personally enrich her. Walter Hewlett (Bill’s son and member of the board at the time) attempted to block the merger that ultimately occurred by the thinnest of voting margins, after which he was not invited back to the board. Fiorina lasted just a few more years until given the “golden parachute” in 2005.

Tom Perkins, the legendary VC founder of Kleiner Perkins Caufield and Byer, resigned from the HP board in May and sent them a letter in August of this year urging a return to the HP Way, “My history with the Hewlett-Packard Company is long, and I have been privileged to count both founders as close friends. I consider HP to be an icon of Silicon Valley, and one of the great companies of the world. It now needs, urgently, to correct its course.”

The company cannot simply return to the past, since it now includes Compaq and doesn’t include Agilent, but it still must choose the way in which it will move forward. This is just another battle in the ongoing war for the culture of HP, and perhaps also for part of the soul of Silicon Valley.

— ed
posted by [email protected]
060908: Silicon Valley's Soul and the HP Board Scandal

Post a Comment

Ed’s Threads 060901
Musings by Ed Korczynski on 1 September 2006

Ethical Discipline and Weasels
Earlier this week, a well-informed individual mentioned to me that many fabs are diluting toxic greenhouse gas emissions instead of properly abating them with plasma-burning or catalytic scrubbers. In certain conditions they fulfill the “letter of the law” while clearly violating the “spirit of the law.” Some may have ignorance as an excuse, but some are just weasels.

Whether directly stealing the fruit of others’ labors, indirectly skimming profit, or maintaining an unearned position of power, I define a weasel as someone who deliberately lies to others for personal advantage. A weasel doesn’t build anything and doesn’t help anyone else. A weasel always takes the low-road in looking for eggs to suck.

David Lepegian while CEO of HPL Technologies used white-out and fax machines to send himself bogus purchase orders …during which time he was trying to sell the company. Now a few years later the technology from HPL—as well as the TestChip technology HPL had acquired—resides with Synopsys so it may again provide value to end-users. For many years, however, the work of many honest technologists was ruined by the poisoned atmosphere left behind by a weasel.

My colleague M. David Levenson reminded me of the tragic case of Jan Hendrik Schon who seemingly falsified data to win and secure a place in one of the last ivory towers. In this case, the peer-review process took a few years to catch the lies. Peers discovered the lack of reproducibility in his experimental results, and also noticed suspicious similarities in data sets purportedly derived from independent experiments. Credulity had been stretched to the point of breaking, and we finally had to recognize that a weasel was in our midst.

There are well established standards of social interaction that guide the behavior of individuals within a group. The expectation of honest personal reporting of one’s impressions of what we like to call “reality” is the entire basis for society. If I trust no one, then at best I end up as a pathetic recluse like Howard Hughes. General Semanticists examine the meaning of language, and they explain that, “The language of a scientific orientation is designed to be factually meaningful, directly or indirectly, and clear and valid. It is intended to satisfy two important tests: ‘What do you mean?’ and ‘How do you know?’”

As in a thesis defense in college, you are responsible for stating your case and arguing your perspective using honest data. You do not have to articulate weaknesses in your arguments, but you must not deliberately mislead by omission. What do you mean when you say that your fab’s exhaust gases are within compliance? How do you measure it? Are you diluting toxic gases or really abating them?

A high-tech industry must be based on rigorous science and driven by disciplined engineering. Both research and development must ensure complete intolerance to infiltration by weasels. They just suck up resources, and then leave a big mess when they’re inevitably caught with egg on their face.

Whenever friends and I discuss the actions of weasels, we invariable reach a point where someone questions what the weasel could have been thinking…how could they have not known that it was only a matter of time before they would be caught? This is logical thinking, and our only conclusion is that weasels must not think logically but instead react emotionally to fear and greed and the other classic negative emotions. It’s good that we aren’t plagued by too many weasels, and we remember to keep checking to purge any that sneak in.

— ed
posted by [email protected]
060901: Ethical Discipline and Weasels

Post a Comment

Ed’s Threads 060825
Musings by Ed Korczynski on 25 August 2006

Moore’s Prediction for Post-Law HOT CHIPS
Nine years ago when I interviewed Gordon Moore, he observed that atomic limits in manufacturing will coincide with the ability to put billions of transistors on a single-chip, and that this huge number would open up completely new approaches in chip design. Such new approaches would allow new functionalities to be deployed without continued shrinks.

The HOT CHIPS 18 conference gathers hundreds of computer scientists and system architects to exchange visions and compare notes. Reconfigurable and parallel computing advances were shown on the first day with truly revolutionary concepts in chip design and function. Ambric is a newish company with a vision for an SoC built out of a 2D array of identical “bric” units, including microprocessors, embedded memory, and cleverly conceived global interconnection hierarchy.

Each bric has eight 32-bit RISC CPUs and 13 KBytes SRAM. Brics connect by abutment through word-wide channels with several levels of hierarchy that can run at up to 10.6 Gigabits per second to form a TeraOPS computing “fabric.” The company’s first chip is an all standard-cell 130nm ASIC made in a general-purpose logic process, with 45 brics in its core array containing a total of 360 CPUs and 4.6 Mbits of distributed SRAM. They claimed this massively-parallel 130nm chip beat a 90nm TI DSP at some benchmark…but it was probably downhill with the wind…

Connex Technology showed a fully programmable HDTV chip, while U.C. Davis showed multiple applications of asynchronous arrays of simple processors. Bernie Meyerson, IBM Fellow and Chief Technologist, provided the big picture perspective on why the limits of classic scaling call for collaborative technology development at all levels. Chips will change to decode video in any encrypted format, and software downloads would deploy new functions.

The result is that some of the current nanoscale processes may be optimized for a particular design and going to the next node may not be the easiest way to add new functionality or reduce cost. Using less exacting design rules allows for less tight integration between design and process, according to Moore (1997): “If you can back off a generation in complexity or performance, then that integration doesn’t need to be nearly as close. If the most advanced technology is not necessarily an advantage…you might as well run the old processes and the depreciated equipment.”

The first decade of the industry saw tremendous innovation, and the transistors/chip doubled every year. The rate of doubling being closer to every two years for other periods is also quite understandable, and clear atomic limits will slow it down. Moore (1997) said, “The update I did on so-called Moore’s Law in 1975 at the IEDM meeting resolved where the improvements had come from previously…we were learning to pack things more efficiently, what I called ‘cleverness.’ We went to isolationless structures, for example. I think we’re looking at the same kind of thing again. So you have the flexibility of what do you do with a billion transistors worth of circuitry. The slope will have changed again, but the industry is certainly not going to stop.”

When Moore’s Law eventually slows—despite Intel’s current 18-month pace—we’ll have billions of transistors with which to play. Hot new reconfigurable designs will exploit the sheer number of transistor to deliver new functionalities to consumers, which will keep silicon running through fabs for decades to come.

— ed
posted by [email protected]
060825: Moore's Prediction for Post-Law HOT CHIPS

Post a Comment

Ed’s Threads 060818
Musings by Ed Korczynski on 18 August 2006

VCs Still Show Us Some Love
Last Sunday, the San Jose Mercury News published its quarterly survey of Venture Capital money going to San Francisco Bay Area firms, and “semiconductors” still gets some of the love. Though, I’m not sure that VCs have entirely shaken off the herd mentality that led to the “Dot Com Bubble.” On the list were no less than 5 startups that plan to help you “search” the internet, and seven companies planning to do something in “social networking”/“dating”/“online community”…which means everybody still wants to have both a Google clone and a MySpace clone in their portfolio. Still, over $250M of VC love went to new “semiconductor” startups in Silicon Valley in 2Q06, so some people are willing to take risks.

Within the category of “semiconductors,” the vast majority of companies are fabless—no surprise. What may be a surprise to some folks is that many of these companies are likely to hire their design engineers outside of the United States. The company headquarters and top executives may be in Silicon Valley, but most of the engineers will be in China, or India, or Romania, or anywhere else. I don’t have any specific inside knowledge on any of the fine companies in this particular list, but this is the general trend over the last couple of years.

I’ve spoken with many Sand Hill Road VCs in the last year, and the unanimous opinion is that paying burdened engineering salaries in the US results in too high a burn-rate, and that equivalent talent can be had for less, so why waste money? It used to be just Silicon Valley and New England and metro New York salaries were too high, so teams had to be spread around the US. But now teams can’t even be located in Ohio (no offense intended to the citizens of the “round on the ends; high in the middle” state).

Depending on your point-of-view, the shift of engineering jobs outside the country either pragmatically results in better final products (considering the individual company), or blindly results in a “race to the bottom” (considering macro-economics). As is often the case, the reality is likely somewhere in between. …lowered development costs can let a greater number of new products come to market, and can make it easier to take risks in developing new functionalities, … but if all companies followed this policy then Silicon Valley as such would fade into history.

Also in recent money news for our industry, Alien Technology withdrew its pending IPO after institutional investors were reportedly less than enthusiastic about the company’s current financial situation. Alien’s is a classic Silicon Valley story: licensed technology from U.C. Berkeley, bold vision for a revolutionary new consumer application, and great success in spending money. Anisotropic etching of silicon can form upside-down pyramids with circuitry on the base, and these micro-pyramids floating in a fluid can flow across a surface with micro-embossed cavities to capture the chips. This claimed 2 million chips per hour technology, termed “Fluidic Self-Assembly,” was an interesting solution-looking-for-a-problem until Alien found the seemingly boundless volumes projected for RFID. History will have to judge their vision.

Perhaps the most significant money news of the week was the seeming success of Frank Quattrone’s appeal in reversing all charges and penalties associated with allegedly showing excessive love toward “Friends of Frank.” This can only be good for more money to flow through the Valley, to again propel the high-tech mills of the clever and/or connected.

— ed
posted by [email protected]
060818: VCs Still Show Us Some Love

Post a Comment

Ed’s Threads 060811
Musings by Ed Korczynski on 11 August 2006

Pain of Knowing Beats Ignorance
Lying on a table face-down, while my leg jumps like a dissected frog’s in response to electrical stimulation, I think about advanced metrology for nanometer-scale IC fabs. I also think about the bizarre pain that’s not overly intense but just feels fundamentally wrong. I don’t recommend doing an electromyogram and nerve-conduction study unless you really think you need it, which I did, after debilitating pain from major nerve-trunks pinched by bulging disks in my lower spine.

The tests provided data, which allowed my doctor to inform me that my nerves are AOK, and that continued physical therapy should be all it takes to complete my healing. (Very good news.) The tests were painful and they took time out of my day, but they were the only way to gain direct information about what was really happening. A lot like the need for more information in leading-edge semiconductor fabs (see last week’s blog, [URL]“Knowing where your atoms be”[/URL])—some people may resist adding metrology steps because they worry about the “pain” or the time involved.

One of the most vital metrics of a semiconductor manufacturing line is the yield “ramp rate”: how fast the percentage of good chips per wafer increases over time. While mature commodity chips may yield in the 90% range, many SoCs and other leading-edge chips may have initial yields well below 50%. Since it costs the fab nearly the same amount to make the wafer regardless of yield (except for test), it’s obvious that ramping as fast as possible is the only way to go.

What holds back yield? These days, due to the concerted efforts of equipment and materials suppliers, the majority of the yield loss is not due to random particles. Things and stuff (technical terms) are really very clean today. Most yield loss today is due to systematic issues: repeatable (not random) defects caused by narrow process windows and specific device topologies. For example, CMP dishing in a lower layer combined with lithography defocus could result in a metal via open every single time.

Systematic yield losses tend to be caused by complex interdependencies which can only be found through extensive data mining. Data that we used to be able to ignore as “2nd-order” and “3rd-order” are now critical information. Companies that accept this reality, and embrace the need for more metrology to produce more actionable information, demonstrate rapid yield ramps at 90nm and 65nm nodes.

Intel, AMD, and TSMC have all shown yield curves indicating that they’ve actually ramped faster as they’ve gone from 130nm to 90nm to 65nm, while other companies report serious problems with yield ramps. Leading companies win by understanding that the game just gets more complex and expensive, and they must invest more simply to keep playing. There will always be companies happy to be followers—many chips don’t need to be made on <180nm node lines, of course—but if you want to play at the high-stakes table, you have to make the big ante.

What does any of this have to do with the nerves in my lower back? At the risk of overly-stretching the metaphor: my pinched nerves correspond to a reduced process window (a very narrow range of pain-free motions), and my habitual movements effecting spinal-disk status are like the complex interdependencies that can degrade yield. With information on the process-window (my nerves), I can reduce guard-banding (i.e., increase movements without fear of injury), which will provide a faster ramp rate (healing). Ignorance is not bliss—it just delays meaningful improvements.

— ed
posted by [email protected]
060811: Pain of Knowing Beats Ignorance

Post a Comment

Ed’s Threads 060804
Musings by Ed Korczynski on 4 August 2006

Knowing Where Your Atoms Be
I had the chance to meet with some of the good folks at KLA-Tencor this week, and they gave me a good overview of the evolutionary changes in metrology for leading-edge semiconductor manufacturing. We must measure ever smaller particles and defects, and combine random defect data with other data-streams to perform yield analyses. Sub-wavelength lithography for complex structures induces systematic layout-dependent second-order and third-order yield losses due to opens and shorts, to name just a couple of examples.

You must ensure high levels of manufacturing yield in multibillion-dollar fabs where the depreciation in capital equipment cost is over $1M per day! Everything is too expensive and too complex to casually react to potential problems, and it’s too late for a re-do when you have to meet the back-to-school selling season. You simply need to know what’s going to happen before it happens. You really want confidence that the new mask-set that’s being delivered will yield well the first time through the line.

One of the fundamental axioms of materials engineering is that to achieve desirable final material properties you must have proper microstructures, which requires controlling manufacturing processes. The more complex properties invariably require more complex structures, which can only be created with more control on manufacturing. Even without the incorporation of new materials, leading-edge ICs today use very complex structures with atom-scale control needed to ensure acceptable final yield.

What used to be a single material is now two phases (i.e., low-k dielectrics with nano-pores). What used to be a homogeneous layer is now complex (i.e., transistor gate dielectrics). And everything must occur within tighter windows. KLA-Tencor shows data indicating that the number of metrology inspections has necessarily increased with the basic complexity of ever smaller manufacturing nodes. The need for more data is felt throughout the line, from mask fabrication to transistor formation to interconnect. Yield enhancement teams need ever more information to keep production moving up the curve.

Coupling between metrology and other production processes invalidates the old mind-set that metrology is not “value-added” like processes that are supposed to move atoms around. While it’s certainly true that moving atoms around is basic to IC fabs (whether by ion implantation, rapid thermal annealing, atomic layer deposition, etc.), it’s significant that we’re now living in a world measured in atoms -- not grams, not even milligrams. To make yielding nanometer-era ICs you must control on the atomic scale, and that means you must measure on this scale. To me, metrology must be seen as an intrinsically value-added function when you need to control the locations of individual atoms, especially considering that just existing at 298°K (room temperature) provides enough thermal energy for atoms to bounce around.

Companies such as Imago (see SST feature article) or the Balazs Labs division of BOC-Edwards (see another SST feature article) provide the ability to count individual atoms in 3D, but these amazing technologies are destructive and unsuitable for routine line-monitoring. Non-destructive metrology companies such as KLA-Tencor, Nanometrics, Rudolph, and n&k (and others) have spoken with me in the last few months about known technologies to provide atomic-scale control in production.

Fab people who grew up in the relatively casual world of >0.25-micron nodes may need to re-examine their concepts about metrology itself. It may sound a bit philosophical, but it’s of the utmost practical importance to think of nanometer-scale metrology steps as vital and intrinsically value-added to production. Besides (as the old saying goes), if it isn’t adding value, then why are you even doing it?

— ed
posted by [email protected]
060804: Knowing Where Your Atoms Be

Post a Comment

Ed’s Threads 060728
Musings by Ed Korczynski on 28 July 2006

DFM Keeps Designers Happily Ignorant
As a manufacturing fab guy attending this week’s Design Automation Conference (DAC) at the Moscone Center in San Francisco, I came away with some insights into the differences between the Design and Manufacturing communities of semiconductor manufacturing. Despite all the talk about walls falling down, the two essential sides of the business still live in completely different worlds.

In a DAC keynote lecture, a luminary recounted the classic stereotype each side imagines of the other (my phrasings): Designers see Fab-folks as hard-hat-wearing bone-heads, while Fab-folks see Designers as air-heads skipping through fields of daisies. IMHO both impressions are loosely based on reality, since many fab engineers probably copy-exactly without thought (i.e., “We use the same cleaning process that we’ve always used.”), and many designers probably don’t understand the concept of a real limitation (i.e., “We still want the best performance, size, and price all at once.”).

“Design for Manufacturing” (DFM) is supposed to be the bridge between the two worlds, and when you dig through all the hype and claims, you find that most of it applies to the mask. Just as the lithographic mask has always been the translation of abstract conceptual space into what we like to call physical reality, the processes associated with mask-making are the focus of most of what’s spun as DFM today.

There were over 40 companies at DAC this year claiming to do DFM: mask data preparation (MDP), optical proximity correction (OPC) and other reticle enhancement technologies (RET), simulation and modeling of both random “critical-area” defects (i.e., particle shorting lines) and systematic “layout-dependent” defects (i.e., CMP layer-to-layer effects shorting lines). Most DFM solutions are post-GDSII, and they entail tweaking the dimensions of individual transistor gates and interconnect lines just prior to MDP. Some cleverly built tools “maintain the designer’s intent” and fix only critical circuit paths.

From a fab perspective, much of this seems like lackadaisical designers are only now dealing with anything other than simple shrinks. How hard is it to constrain a pitch to avoid most opens and shorts between lines, or to double-check that vias will connect no matter the variation in lithography or etching, or to avoid clustering the hottest transistors all together in the same area of the chip? These sorts of DFM solutions seem pretty obvious, though I’m sure they can be daunting to implement properly and I’m sure that EDA software development engineers work very hard. But from my perspective, Designers live very spoiled and pampered existences compared to Fab-folks.

Using sub-wavelength lithography and atomic-layer depositions of thin films to make nanoscale circuits with billions of active elements across single-crystal silicon with high yield is truly amazing work. It’s tough stuff - really, really tough. By the way…hard-hats don’t fit inside bunny suits, and just sustaining one tool in a 90- or 65-nm node CMOS production line requires multiple engineering disciplines. The fundamental technology development needed for 45nm and below nodes includes strained-SOI wafers, exotic metals, and hetero-epitaxial atomic layers – requiring the extraordinarily challenging materials engineering that has been on-going for decades. The great semiconductor industry era-of-the-shrink occurred only because of continuous engineering innovations in manufacturing.

Designers don’t want to know about any of this; they want to remain completely ignorant of optical physics and materials science. EDA tools have already liberated Designers from ever having to think about the real world of gate dielectrics and metal contacts. The EDA companies continue to give their customers what they want. Now DFM promises continued happy ignorance for Designers…but someone better check on how those new models are calibrated.

— ed
posted by [email protected]
060728: DFM Keeps Designers Happily Ignorant

Post a Comment

Ed’s Threads 060721
Musings by Ed Korczynski on 21 July 2006

Options, Options, Who’s Got the Options?
Unless you’ve been in a media blackout or too busy getting real work done to ever read a newspaper, you can’t help but hear about the “Stock Options Backdating Scandal” (>200,000 Google hits in early September) tsunami now breaking upon the shores of Menlo Park. The apparent habit of many Silicon Valley companies to backdate stock options grants is now under scrutiny. If you aren’t fully up on the topic, take the time to read up on stock options, strike price, and backdating at any mainstream media source.

I’m a technologist, not a lawyer or a bean-counter, so I can’t meaningfully comment on the law in general or how specific companies may have skirted the law. But having lived and worked in Silicon Valley for most of my life, I can comment on stock options as part of the lifeblood motivation for technologists in our industry. Put simply, stock options were a way to reward employees for the ridiculously long hours they committed to grow start-ups.

Earlier this year I listened to a panel of VCs discussing the team environment of a startup, and their unanimous opinion was that anyone interested in work-life balance and less than 70 hours/week of work had no business being in a startup. The expectation in Silicon Valley has always been to “shoot the moon” with a revolutionary new technology, and success in the marketplace occurs always and only with 80+ hours/week of work. “Yeah, I’m going to need you to go ahead and come in again this weekend.”

There used to be secretaries to top executives at start-ups who’d make millions on stock options, but those days are long gone.

The silicon IC manufacturing industry, including OEMs and specialty materials suppliers, is now mature. As a company or industry matures the potential for revenue growth slows, and since stock price is typically based on forward-looking estimates by analysts, a mature industry just won’t see the rapid rises in stock prices that used to result in stock-splits. Despite all the tap-dancing done to entertain analysts, it’s likely that the vast majority of companies in our industry will not be forecasted to double or triple in value. Consequently, stock options only turn into millions of dollars when they’re given out in massive quantities to top executives.

Engineers and front-line managers may be lucky enough to get a few thousand shares…which could turn into down-payments on new cars. Directors may get a sufficient number of shares to make differences on their tax returns. Top executives now seem to keep most of the shares (as rubber-stamped by the compensation committee), which they justify as just rewards for their enlightened strategic direction, which is fine if the direction is truly outstanding. Of course, outstanding direction should lead to out-performing one’s competitors which should result in stock price increases so there’d be no need for backdating, would there?

I expect minimal disruption to our industry and its current business models…though costs for accounting and financial records inspections will probably increase. The few actual start-ups in the chip business these days can still use stock options to incent employees, and assuming real growth in value there should be no reason to consider backdating, should there?

— ed
posted by [email protected]
060721: Options, Options, Who's Got the Options?

Post a Comment