Ed’s Threads 070129

Musings by Ed Korczynski on January 29, 2007


Intel wins race to be Intel
How did it happen? How could Intel present 45nm transistor results with high-k dielectrics and dual metal gates (HK+MG) years ahead of everyone else? Mark Bohr, Intel senior fellow in logic technology development, stated, “I don’t believe any other company will have high-k and metal gates until the 32nm node or later.” If this is true, it is only because IBM and other companies felt that they wouldn’t need HKMG for 45nm so they did not start manufacturing work two years ago. Thus, Intel has won a very difficult race as the single contestant.

It seems that the company even surprised itself with these results. On Thursday Jan. 25th, the day before the official announcement, Intel invited journalists to a last-minute show-and-tell at its Robert Noyce HQ building in Santa Clara, CA. PCs running on 45nm “Penryn” chips were shown—all of which came from the “first-silicon” wafer with these new materials processed using the first mask-set. Packaged first-silicon chips received at Intel’s Folsom test lab at 1:00 am had functioned, and the team immediately rushed one into a motherboard which promptly booted a software OS two hours later. Intel showed a photo of the team toasting their success with Martinelli’s sparkling cider at 3:00 am—give Intel credit for maintaining entrepreneurial zeal with nearly 100,000 people.

Two core competencies were at work to get to these results: extreme discipline in manufacturing execution, and proprietary design and yield-learning methodologies. Since Intel has always had to live in the brutal merchant market, it has always aimed for the sweet spot in the middle of manufacturing-cost and chip-performance, and then relentlessly driven to meet its goals. Instead of silicon-on-insulator (SOI), Intel pushed traditional planar transistors on bulk silicon wafers to the limits of traditional materials for its current 65nm node manufacturing.

Looking at 45nm options about two years ago, Intel decided to stick with bulk silicon wafers and add HK+MG. In Jan 2006 it announced yielding SRAM TEG chips with >1B transistors, but kept secret that these chips used HK+MG. Still secret is the hafnium-based dielectric composition, both of the metal gate materials, and whether the process flow is “gate-first” or “gate-last.” The new transistors still maintain strain in the channel regions for maximum carrier mobility. Innovative design rules and advanced mask techniques will be used to extend the use of 193nm dry lithography, which we may assume includes orientation limitations in harmony with illumination sources. All these changes result in new process integration challenges and new yield-loss mechanisms, so we might expect it to take a while longer to ramp yield. Amazingly, Intel shows a 45nm yield-learning curve that tracks the last three nodes (see figure, above).

CEO Paul Otellini—dressed all in black like an international jewel thief, perhaps due to having spent excessive time around Steve Jobs—stated, “The plan is to have microprocessors in end-users hands by the end of 2007.”

Meanwhile, with timing that just could not be coincidence, on January 26th SEMATECH announced R&D; of a gate-first HK+dualMG process. “Be aware of the difference between a real manufacturing commitment, and research papers that continue to fall short of these results,” stated Intel's Bohr. The very next day IBM/AMD/Sony/Toshiba said that they will use HK+MG with their 45nm transistors sometime in 2008. We may assume that this announcement was rushed out in response to the Intel press release, since it erroneously refers to HK+MG as a single material—either the IBM alliance plans to use only one of the two, or IBM needs a technologist to review their press releases.

Technology development continues in the industry. Intel’s use of HK+MG materials in mainstream 45nm commercial manufacturing is certainly a significant milestone. Certainly other companies will follow, though in their own ways and in their own times. Due to the extreme complexities involved in any nanometer-era IC manufacturing, it’s getting more and more difficult to compare results from different companies. Fortunately, you can trust SST and WaferNEWS to sort the reality from the hype.

— E.K.

Labels: 45nm, high-k, HK+MG, IBM, Intel, metal gate, semiconductor

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070129: Intel wins race to be Intel

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Ed’s Threads 070116
Musings by Ed Korczynski on January 16, 2007

HP’s crossbars pay three nodes early
HP’s bet on 30 very smart people and modest lab space for a decade seems to have paid off early. R. Stanley Williams, senior fellow at HP Labs and founding director of the HP Quantum Science Research (QSR) group, has led this brain-trust since 1995. Nano crossbar arrays have been considered for far future memory and logic, but now they’re unveiled as a new 15nm-width field programmable nanowire interconnect (FPNI) circuit concept that may see production in 2010 along with 45nm node technology…three nodes earlier than anyone expected!

On a beautifully grey Winter Solstice day in Palo Alto, M. David Levenson (editor of MicroLithography World) and I joined SST senior technical editor Debra Vogler to meet Williams and his team and tour their lab. I saw enough evidence to support this three-node-jump claim for their nano crossbars. This novel circuit architecture appears to be both manufacturable and scalable, with what seem to be only two new unit processes: nano imprint lithography (NIL) for the bar formation, and the spin-on/etch of the molecular switching layer. Modeling of FPNI circuits show functionality with scaling down to 4.5nm-wide crossbars.

Team members Philip J. Kuekes, Shih-Yuan Wang, and Wei Wu provided us with a fantastic tell and show: discussion of crossbar architectures and fabrication processes, followed by a tour of the lab with the cool custom equipment. HP is one of the few large companies that still supports fundamental R&D for the industry, and the company creates multi-disciplinary teams comprised of systems/information theorists, circuit designers, physicists, chemists, and mechanical and materials engineers.

“One of the interesting things about HP is that it’s a big company that has re-invented itself,” commented QSR computer architect Kuekes. Teams continue to invent new device structures as well as research the processes, materials, and equipment necessary to form them. For example, there’s a trade-off between the manufacturing precision in the CMP step and the system design complexity to handle variability, and HP has all the brains needed to quantify trade-offs. “We have an amazing number of people from different disciplines,” said Kuekes. In the end, they had some physicists measure and model the physical platen in the CMP tool and then affix precise weights around the rim to “balance” it like a wheel on your car.

They also built their own NIL tool, and they are currently working on the 5th generation. Mask formation can be quite complex using MEMS-like processes to achieve special frequency doubling. Any NIL process and hardware IP will probably ultimately be licensed out, since HP isn’t in the equipment business. (David Lam was working on process control for plasma etching with HP the late 1970s, but HP did not want to get into the equipment business, so he left on good terms and then formed Lam Research.)

One of the great aspects of the crossbar design is that none of the manufacturing control has to be perfect—bars are expected to fail, and signal multiplexing through redundant lines compensates. Prior reports had indicated that 11 lines of a generic crossbar array could have 10% random failure and still guarantee 100% signal transmission of an 8-bit-wide multiplexed data stream. For FPNI circuit applications, HP’s models show that a crossbar array with 20% randomly failing lines should still provide 75% chip yield.

The bottom electrode is platinum, while the top electrode is platinum over titanium. Forming the cross connections between the orthogonally aligned top and bottom bars are molecular monolayers. The monolayer is blanket deposited over the patterned bottom electrodes, and then etched using the top electrodes as the mask. Each cross-junction is a resistive memory element within an array that can function as a memory or latched-logic circuit, or an FPNI.

Both electrodes are formed by lift-off lithography using dual-layer resist. “People do not know how to do platinum etch,” reminded QSR scientist Dr. Wu, “so we have to do a lift-off process.” The top “imaging layer” of resist is formed by NIL. E-beam direct writing with 60nm pitch is used for NIL mold fabrication, but some tricks allow doubling of the spatial frequency along with dual e-beam writing so that they can achieve 30nm pitch today. Then the bottom “transfer layer” resist is formed and undercut by sequential isotropic and anisotropic RIE. The undercut is essential so that the sidewalls are not coated by metal PVD, which allows for clean lift-off of the metal on top of the resist when the resist is stripped. “That’s how we can get crossbars with much higher yield,” commented Wu.

It’s worth noting that lift-off was a standard way to form metal interconnects back in the 1970s when linewidths were multiple microns. In all lift-off processes, the metal deposited between resist lines remains in place, while a wet solvent dissolves away the resist such that any metal on top just floats in the strip solution. This is a bit of an inherently messy situation, and stripper flow and filtering must be properly managed so that these bits of metal do not drop onto the wafer surface as defects. Still, with proper control of the resist to eliminate any sidewall deposition, lift-off patterning can be highly robust and manufacturable.

We don’t really know any of the details about the processing of the molecular monolayer, but we may suspect that its final form can sustain the temperatures used in standard packaging processes. Since the array is the top-most layer in the FPNI design, the monolayer need not be compatible with the 400-450°C standard used in the lower interconnect processing. Working FPNI chips aren’t expected for a year, and there are certainly many details to be resolved before the anticipated 2010 manufacturing debut of nano arrays. but the crossbar prototypes seen in the lab look good. I’d bet on it working.

—E.K.
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070116: HP's crossbars pay three nodes early

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Ed’s Threads 070105
Musings by Ed Korczynski on 2007 January 05

Infineon doesn’t fancy 45nm finFETs
I’ve got fins on the brain these days.

My Dec. 8 blog entry covered finFET information presented at IEDM 2006 which included the common consensus that they would not be ready or needed for 45nm. Then I interviewed Dr. Klaus Schruefer, principal scientist for CMOS devices at Infineon Technologies, and wrote in my Dec. 15 blog entry that “Infineon fancies 45nm finFETs” for LSTP circuits.

A representative from Infineon subsequently contacted me to say that I’d mistakenly read between the lines in Dr. Schruefer’s comments, and that Infineon agrees with the rest of the industry that finFETs will not be used for 45nm node low-standby power (LSTP) circuits.

Infineon still asserts that for state-of-the-art LSTP digital circuits, finFETs provide equivalent performance to planar transistors with 1/10th the leakage current, the costs of manufacturing are nearly identical, and these chips should consume one-half the battery power. However, Infineon insists that, “there is still a long way to go to adopt such a revolutionary technology. One has to demonstrate manufacturability at 32nm dimensions.”

Since any fundamentally new manufacturing technology is expensive to develop, companies need to be able to deploy the technology over many nodes to recoup the investment. However, proving manufacturability can lead to a logical Catch-22: you can’t use it until you know it will work, but you don’t know it will work until you use it.

There is always risk in anything new, but there are also rewards. The decision on whether to accept a new manufacturing risk depends on the anticipated rewards, and the only way to estimate those is to rely upon approximations and models from R&D; tests. There’s an old concept in manufacturing that you should never accept any risk unless the promised reward is substantial—such as at least doubling a fundamental metric like yield or performance.

Infineon has shown that for nearly equivalent manufacturing costs (certainly only modelled estimates at present) they can use finFETs for LSTP chips that should consume ½ of the battery power. Consumers don’t care about transistor architectures, but they sure care about battery life in cellphones, portable game players, PDAs, and iPods. Yes, displays suck battery life too, but chips dominate in many cases.

How great are the risks associated with transitioning from “planar” transistors to finFETs? There could be utterly unprecedented yield losses due to currently unfathomable interdependencies. There could be problems with metrology for in-line process-control of new structures. Any number of issues could arise. Yet if relatively standard unit-processes are combined into new process modules, and the estimated manufacturing cost is <3% greater than a baseline, then it’s hard to imagine intractable yield issues.

The current consensus is that finFETs may be first used at the 32nm node. But if they provide double the battery life for portable MP3 players, then why not deploy them earlier at 45nm? Is it really already too late to choose a new 45nm LSTP transistor manufacturing technology? Or are many companies secretly planning to deploy finFETs for 45nm LSTP, while they all publicly proclaim the opposite? Is this a key new strategic inflection point? I’m open to the possibility. As Intel’s Andy Grove has said, “Only the paranoid survive.”

— E.K.
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070105: Infineon doesn't fancy 45nm finFETs

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