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070803: Intermolecular blazes new trails for labs and fabs
Ed’s Threads 070803
Musings by Ed Korczynski on August 03, 2007

Intermolecular blazes new trails for labs and fabs
Intermolecular, which officially decloaked at this year's SEMICON West, has taken high-productivity combinatorial (HPC) technology from a Symyx license and added test-chips/parametric-testers and informatics software to revolutionize the way new materials technology is developed in labs and deployed in high-volume fabs. Intermolecular works to provide faster time-to-market, at lower cost, and lower technology risk. Symyx’s license to Intermolecular includes the IC space, FPDs, bio-chips, MEMS, and any combination of active and passive circuit elements on a planar substrate.

Subtle differences between R&D; and process chambers mean that subtle materials properties can change final device results. Thus, while basic materials research can be safely done on R&D; tools, unit process development and subsequent process integration have to occur with high-volume manufacturing tools. These production systems are typically not flexible, and changing materials and parameters can be so slow that an experiment can take from an hour to a day to run.

“The majority of the $20+ billion in annual technology development for the industry is spent in process integration,” said Intermolecular founder and CEO David Lazovsky, in an on-site interview with WaferNEWS. Thus, Intermolecular’s ~700 applied-for patents deal with the three basic technology development stages of the industry:

-- Materials research, performing 500 experiments/wafer of basic materials properties;
-- Unit process development, reproducing 100s of processes/wafer on customer production wafers; and
-- Process integration, doing 10s of experiments/day that output parametric/wafer-level reliability (WLR) data.

The company has invested substantial resources to increase staff up to ~70 people with backgrounds in process, equipment, test-chip design, software, and surface chemistry. Investment in lab space and hardware has led to unique tools to process full wafers and also rectangular silicon “coupons,” parametric testers, and an Applied Materials’ Endura PVD tool that allows for correlation experiments between combinatorial modeling and high-volume production tool performance.

“Gradients are terrific if you’re just looking for materials properties. But at the device level for the IC industry, having a gradient across the device won’t be of any use,” explained Lazovsky. "What we enable is discretized processing so you have control over an area like you would in a high-volume processing system."

Using high-volume production tools for development has always been a bottleneck, but with the plethora of new materials interactions to be tested for 32nm node IC manufacturing, there’s a tipping point. What's needed is far more than a mere doubling or trebling of efficiency -- we need orders of magnitude faster results.

Intermolecular's Tempus F-20 tool performs fluids experiments using arrays of beakers/pipettes and silicon coupons for early and middle stage screening experiments with hundreds of splits simultaneously. The Tempus F-30 (used for latter stages of screening) performs fluids experiments on full 300mm wafers, using an array of tiny (~1-in. dia) circular chambers with Teflon seals to provide 28 different experimental splits across a wafer (see figure below).

For example, with parallelism a full wafer can be processed through the following four sequential wet steps in just four minutes using a parallel processing station and an adjacent blanket processing station:
-- Pre-clean,
-- Self-assembled monolayer dep.,
-- E-less cobalt dep., and
-- Post-clean.

For integration work, a customer (or a customer’s customer) provides patterned wafers pulled from a fab line. After combinatorial depositions, parametric testers can extract device data from each of the 28 discrete splits.

The self-assembled monolayer is a molecular masking layer (MML), a novel molecule synthesized specifically to bond to various low-k dielectric films, and provide a uniform top surface for an electroless deposition. The MML was synthesized after 7635 experiments with 60 molecules ran on 25 wafers in 5 weeks…and at the end of electrical tests they found two molecules that had some of the right properties. One of these was the basis for synthesizing a new precursor for a materials supplier customer that is a low viscosity liquid at room temperature.

As another example, Intermolecular helped a leading Taiwanese foundry develop a wider process window for interconnect cleans for the transition from the 65nm to the 45nm nodes.

Fluids-based processing hardware is available for sale and license along with support. PVD tools are internally developed for collaborative development programs, and will be productized for sale as hardware like the fluids tool. ALD is on the company's roadmap.

Since Intermolecular focuses on integration, investments in test-chip design software and parametric test hardware allow for sophisticated optimizations of circuit functions. Working with partially processed wafers, Intermolecular rapidly screened >12,000 sets of flash memory cells using PVD, followed by additional screening to optimize the read/write pulses to match the properties of the new cell. “So there are combinatorial methods used to develop the materials system, and there’re also combinatorial methods used in how you operate the cell. That’s part of the solutions space, and it’s non-trivial,” commented EVP of business development Gustavo Pinto.

Intermolecular seems to have found a truly new and powerful methodology to integrate new materials into advanced ICs. With the ability to do deposition experiments on at least 28 discrete areas of a wafer and then test and extract productive information from massive data dumps, you can get a lot of work done. Rarely is the use of clichés like “paradigm shift” or “revolutionary” justified…but this might well be one of those rare cases.


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070803: Intermolecular blazes new trails for labs and fabs

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.