Ed’s Threads 080211
Musings by Ed Korczynski on February 11, 2008

IITC process units and integration
The International Interconnect Technology Conference (IITC) has issued its 11th call for papers, and for a change it will explicitly focus on unit processes (and new materials) while continuing to cover the leading edge of integration. The main deadline for paper submissions has now passed, but a limited number of late papers will be accepted until April 11th. The shift in emphasis toward covering unit processes is due to the divergence of integration options moving forward.

Manufacturing ICs on silicon wafers is very complex; hundreds of “unit process” steps (e.g., clean, inspection, etch, deposition, etc) are combined into dozens of “integrated process modules” to form functional structures. One integrated process module may form high-performance transistors, another module forms contacts to transistors, and yet another module forms interconnects between contacts. Many of the unit process steps are copied between modules, and thus has it been since the 1960s.

During the last twenty years, the digital CMOS shrink has been the one process integration direction uniting all the different unit processes under development. The set of requirements for the next node/generation of digital CMOS was always the most challenging for equipment manufacturers working on unit processes. However, starting with the 45nm node, the integration of unit processes has become so complex that there is no one obvious solution for all fabs.

Dr. Thomas Caulfield, EVP of sales, marketing, and customer service for Novellus Systems and former technology executive with IBM, talked with WaferNEWS about the changes in the development of unit-processes in the industry. “As an industry becomes commoditized, how to you differentiate? You either have more efficient design, or more efficient unit processes that allow you to get more productivity or functionality out of the manufacturing. So the last thing you want is the same integrated process,” explained Caulfield. With the leading-edge of IC manufacturing ever increasing in complexity, the productivity of tools used in the fab must increase just to keep costs the same.

Consider the process module to form contacts as an example of integration. Today, the formation of advanced contacts requires something like the following sequence of unit processes:

1) CVD of a blanket dielectric layer,
2) Thermal treatment to stabilize/planarize,
3) Metrology to inspect the layer,
4) Photoresist mask spin-on and bake,
5) Lithography to form initial openings,
6) Treatment to shrink the opening,
7) Metrology to inspect the photoresist,
8) Etch of the dielectric through the mask,
9) Strip/Ash the remaining photoresist,
10) Clean/Treat the dielectric openings,
11) Metrology to inspect openings,
12) Deposit metal barrier layer,
13) Deposit metal for contact,
14) CMP of metal layers, and
15) Metrology to inspect contacts.

Each of these steps has sub-steps too.

In the past, major developments could be described and documented at the integrated process module level, allowing much of the unit process details to be IP secrets. The amazing innovation that enabled digital CMOS shrinks is now pushing against limits of atoms and wavelengths of light, and it now seems clear that further pushes will be ever more expensive. Fabs will also work to integrate analog, RF circuitry, integrated passives, and 3D packages using essentially the same unit processes. “It’s no longer Moore’s Law one-size-fits-all with all the focus on the next generation technology,” explained Caulfield.

Since the integrated process details are now quite sensitive, technologists are relatively more able to talk about developments in unit processes. From an equipment supplier perspective, of course, unit process development does not occur in isolation. “You develop a process capability because you have an application and market in mind,” explains Caulfield. “It’s not that we don’t keep doing that, but today we find customers using the same unit processes in novel ways.”

EDN’s Ron Wilson recently blogged about the IITC call-for-papers and the ramifications of unit process development for IC designers. He considers that porting a physical design from one fab to another may soon require significant inputs from equipment manufacturers, but it is highly unlikely that designers will ever have to talk to OEMs about GDSII files. Using the example of the contact module, the variations in the geometry of the metal contact plug are due to the interdependencies between the different unit processes. Sometimes the source of a structural variation can be easily identified as one unit process, but more often it is impossible to separate out which of the unit processes were to blame. If the diameter of the contact is too large, was the resist overexposed, or was the dielectric overetched?

In addition to the complexity that can be seen in final device structures on the atomic-scale, there are many sacrificial thin-film layers and other “hidden” unit processes within the integrated flow. “It’s funny to watch people debate how something was done based on the data from reverse engineering a final chip,” commented Caulfield. “There’s just no way to conclusively determine the process sequence afterwards with so many sacrificial steps in the integration scheme.”

For example, Novellus sells a pseudo-ALD dielectric tool that forms what they call a pulsed-deposition layer (PDL). Some DRAM fabs use a sacrificial dielectric which they remove with a wet etch, and for this integration scheme the PDL provides no advantage. However, other DRAM fabs use CMP to remove the equivalent sacrificial dielectric, and for them the PDL provides an advantage. The reasons for choosing one integration approach over another are very complex. “People are leveraging unit processes in different ways to try to get the best results while going to higher density,” explained Caulfield. “Productivity or manufacturability differentiation through proprietary integration schemes is the goal—and there are many ways to skin the cat—that provides competitive advantage.”

OEMs have always sold tools that perform basic unit processes, and fabs have always fine-tuned unit processes for integration into modules. The only fundamental change now is that fabs must manage extreme complexity at the same time that most chips have become commodities. “It’s a big problem that the industry is adding manufacturing complexity at the same time that chips are becoming commoditized,” expressed Caulfield. “If you’re not on a curve to take cost out of running a manufacturing tool, then you’ll become the problem that gets worked out of the equation next.”

—E.K.

Labels: CMOS, IITC, integration, OEM, PDL, process, unit

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080211: IITC process units and integration

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