Ed’s Threads 071130
Musings by Ed Korczynski on November 23, 2007
PV perspective: Interview with AMAT's solar technology expert
Dr. Charles F. Gay, currently VP and GM of Applied Materials’ solar business group, is a renowned expert in PV technology and business, having been president of Arco Solar, Siemens Solar, and ASE Americas, as well as director of the US Department of Energy’s National Renewable Energy Laboratory (NREL) in Golden, CO. He found time in his busy schedule to talk with me about the incredible growth in solar business, and to explain recent changes in the photovoltaic (PV) technology landscape.
“The speed of innovation has ratcheted up quite rapidly, and there are two themes that have affected the industry over the last several years,” explained Gay. One is the scale of the industry, growing at over 40% over the last decade. This has created a dynamic where a company like Q-Cells can just show up in the market and rapidly rise to be No.2. Suntech at No.3 was virtually nonexistent three years ago.
Secondly, as the business has grown, so has the scale of manufacturing. Until recently, crystalline PV lines mainly ran old 150mm wafer equipment obsoleted from IC lines by newer 200mm tools. Less than a decade ago, a world class PV line was capable of producing fewer than 5MW/yr of cells, while today Sharp alone has over 700 MW/year of total fab capacity. Typical PV lines today are 50-100 MW, and a company wanting additional capacity builds multiple lines on site, or starts locating lines around the world depending upon customer demand.
A 100 MW/year line needs to process such a large area of material that equipment from industries other than IC manufacturing, like FPD or architectural glass, have come into mainstream use. “The process control was there, the history of making machines was there, and the expertise enabled thin-films to come onstream just when the lack of silicon had been threatening a delay in continued growth,” Gay said. Control of uniformity over large areas allows for potential cost-reduction in thin-film PV lines.
Thin-film PV panels have been able to capture an increasingly larger piece of the market. While still only ~10% of the total, it is expected to grow at a faster pace due to sheer economies of scale using large glass panels. Secondarily, thin-film lines may take extra market share while crystalline silicon line production is limited by the near-term global poly-silicon shortage.
Some crystalline solar manufacturers have responded with innovative materials engineering and supply-chain management. Using gettering, diffusion, and blanket etching of a top sacrificial layer, a PV line can essentially pull most of the impurities into a top skin that is removed. This adds fab cost, but allows for the use of less expensive "six-nines" [99.9999%] pure starting silicon that is not in short supply. “People thought maybe we can make silicon from dirty quartz using direct reduction, and maybe the silicon only needs to be six-nines pure, instead of nine-nines,” Gay said. He added that cell efficiency for single crystal is ~22% for the very best quality starting material and fab process, ~18% is a general capability for single crystal silicon, and ~16% for high-purity multicrystalline silicon.
Another example of clever materials engineering in PV is tuning the sheet resistance of the silicon using phosphorous (P) diffusion that is pattern dependent. The spacing of topside aluminum lines is determined by the sheet-resistance of the silicon after P diffusion, but P dopants interfere with the short-wavelength absorption of light. An optimization can be found by tuning the P to be higher under the lines (for reduced contact resistance) and lower between the lines (increasing conversion efficiency).
“Innovation has been happening at a faster pace due to the increased scale,” said Gay. “The size of the market is enabling additional R&D in academia, industry, and government, and also allowing for leaps in manufacturing efficiencies.”
An example of manufacturing efficiency increasing with scale is the production of “water-white” glass panels for thin-film PV. Water-white glass has low concentration of Fe2O3 which increases optical transmittance, and results in ~2% more light transmission, explained Gay. However, the global demand for this specialized glass was relatively small, so it was only made in relatively expensive batch furnaces. A few years ago, based on solid demand forecasts for thin-film PV panels, architectural glass companies such as Pilkington, PPG, Cardinal Glass, Asahi, etc. started retrofitting continuous float-lines for water-white production. Glass companies can sell “water-white” glass for a premium over standard green soda-lime, while still offering a cost reduction that could be cents per square foot compared to batch processing.
“All the way across the value chain, from basic science to the infrastructure for installation, there is tremendous activity in solar,” observed Gay. “It’s multiplied to the stage in Germany today there are almost as many jobs in solar as there are in automotive. Solar and wind represent for the first time in history the opportunity for job creation.”
With the global terawatt challenge remaining ahead of us, there’s lots of work to be done.—E.K.
Labels: business, energy, manufacturing, photovoltaic, solar
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071130: PV perspective: Interview with AMAT's solar technology expert
Ed’s Threads 070427
Musings by Ed Korczynski on April 27, 2007Planning for life after CMOS commoditization...todayIt’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending
this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s.
Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors.
In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP).
Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon.
Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all.
With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan.
IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs.
Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day.
— E.K.
Labels: business, CMOS, commodity, fab, IC, strategy
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070427: Life after CMOS commoditization
