Ed’s Threads 080512
Musings by Ed Korczynski on May 12, 2008

SAIL to fly at 5 meters/min
The highlight of the April 16 North California Chapter of the American Vacuum Society’s (NCCAVS) Thin-Film Users Group (TFUG) meeting on printable electronics was the detailed technology presentation on self-aligned imprint lithography (SAIL) as developed by HP and PowerFilm Solar for their roll-to-roll (R2R) IC line. Many other companies are also developing real ultra-low-cost ICs and sensors using micron-scale printed thin-film transistors (TFT).

Palo Alto Research Center, Inc. (PARC, now independent from Xerox) working with Stanford University and Cabot Microelectronics recently won a DARPA contact to develop light-weight, inexpensive sensors using printing technologies. The basic technology uses printed TFT materials with all processing done at <200°C to allow for compatibility with plastic substrates, and should be applicable to the monitoring of pressure, acceleration, temperature, and chemical exposure.

PARC’s Ana Cladia Arias discussed methods used to deposit and integrate solution-processed materials using ink-jet printing. They have developed a complete additive process for the fabrication of simple prototype TFT backplanes on glass and on flexible plastic substrates. Surface energy control of the polymer gate dielectric layer allows printing of the metal source-drain contacts with gaps as small as 10μm. Silver nanoparticles are used in the ink that forms gate and data metals. The I_ON /I_OFF ratio is ~105, and TFT mobility of 0.05 cm²/V·s were obtained.

Ink-jet printed electronics promise relatively low-cost manufacturing. Another highly customizable printing approach is the dip-pen technology developed by NanoInk for different applications. None of these technologies, though, could compete in cost and throughput with the rotating drum of a printing press, and so other companies are looking at ultra-low-cost patterning on roll-to-roll (R2R) substrates.

As mentioned in Tom Cheyney's recent flexible electronics article for SSTsister publication Small Times, Hewlett-Packard Laboratories (Palo Alto, CA) and PowerFilm Solar (Ames, IA) are working toward large-area arrays of TFTs on 330mm wide polymer substrates using exclusively R2R processes. Ohseung Kwon of HP Labs explained some details of the SAIL process which allows for 100nm feature alignment across a roll moving at >5 meters/min. Prototype work has been done

By encoding the geometry for all of the patterning steps into discrete heights of a 3D masking structure, the SAIL process borrows from the experiences of the MEMS industry in multilayer hardmask integration. All mask-formation is done before any etching, so that alignment is maintained regardless of process induced substrate distortion. Using a 100mm wide polyimide substrate (Kapton brand) for prototyping the UV-curable NIL process, they have achieved 4 imprint levels in 0.5μm step heights.

To form the TFTs, five blanket layers are deposited sequentially to form a stack, with no deposition temperature >260°C: PowerFilm had already developed PECVD for nitride and oxide as part of a-Si:H PV fab R&D for DARPA. HP Labs contributed their house-built R2R coater. The complex thin-film stack is as follows:
* Al gate metal,
* SiNx dielectric,
* a-Si semiconductor,
* n+ micro-crystalline-Si contact, and
* Cr top metal for source/drain.

Then the SAIL layer is formed, careful resist ashing allow for 3 or 4 layers with unique patterns to be exposed as masks. TFTs with on-off ratio >E7 (with dimensions 40μm × 2μm or 100μm × 1μm) have been printed.

The etching integration with this self-aligned mask is understandable challenging. Most are wet and use home-brew tooling, but some need to be dry plasmas. The wet etch system is 1/3 meter wide and can separate source/drain areas from gate areas at 1.5 meters/min. “If you can achieve the etch undercut very well, everything else can be done in a planar manner,” said Kwon regarding the complex multi-step etch flow.

R2R Plasma etching technology is challenging…to start with there is no “end-point” as commonly considered in wafer etching systems. Transferring the substrate from atmosphere to vacuum is achieved by load-locks for each roll that becomes sort of a batch. These are certainly not continuous processes. “Since we are using this kind of roll, once the surface is rolled up it serves as its own cleanroom,” explained Kwon.

—E.K.

Labels: electronics, litho, printed, R2R, roll-to-roll, SAIL, TFUG

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080512: SAIL to fly

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Ed’s Threads 070413
Musings by Ed Korczynski on April 13, 2007

MRS meeting specs the future
The Materials Research Society (MRS) spring meeting was in San Francisco April 9-13, and the near- and far-term possibilities for process technology in our industry were presented to a record numbers of attendees. Researchers showed results from the world’s leading labs for electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes. It’s like sipping from a firehose, unless you’re interested in just one of the 36 parallel sessions.

Sachin Joshi of UT-Austin showed that hybrid-orientation technology (HOT) silicon wafers based on the MEMC direct silicon bonding (DSB) approach contain inherent defect-rich junctions between orientations. Shallow-trench isolation (STI) regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Non-silicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.

Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8 x 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.

An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel's Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.

Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties—elastic response (including lateral coupling across the pad), slurry transport, and average asperities—he showed how chip-scale uniformity can now be predicted.

Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria-slurries. A counter-intuitive “slow start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5X lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.

MRS meetings also cover wilder technologies like superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of sea-shells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.”

— E.K.

Labels: electronics, materials research, modeling, nano, self-assembly, silicon

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070413: MRS meeting specs the future

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