Ed’s Threads 080512Musings by Ed Korczynski on May 12, 2008
SAIL to fly at 5 meters/min
The highlight of the April 16 North California Chapter of the American Vacuum Society’s (NCCAVS) Thin-Film Users Group (TFUG) meeting on printable electronics was the detailed technology presentation on self-aligned imprint lithography (SAIL) as developed by HP and PowerFilm Solar for their roll-to-roll (R2R) IC line. Many other companies are also developing real ultra-low-cost ICs and sensors using micron-scale printed thin-film transistors (TFT).Palo Alto Research Center, Inc
. (PARC, now independent from Xerox) working with Stanford University and Cabot Microelectronics
recently won a DARPA contact
to develop light-weight, inexpensive sensors using printing technologies. The basic technology uses printed TFT materials with all processing done at <200°C to allow for compatibility with plastic substrates, and should be applicable to the monitoring of pressure, acceleration, temperature, and chemical exposure.
PARC’s Ana Cladia Arias discussed methods used to deposit and integrate solution-processed materials using ink-jet printing. They have developed a complete additive process for the fabrication of simple prototype TFT backplanes on glass and on flexible plastic substrates. Surface energy control of the polymer gate dielectric layer allows printing of the metal source-drain contacts with gaps as small as 10μm. Silver nanoparticles are used in the ink that forms gate and data metals. The ION
ratio is ~105, and TFT mobility of 0.05 cm2
/V·s were obtained.
Ink-jet printed electronics promise relatively low-cost manufacturing. Another highly customizable printing approach is the dip-pen technology developed by NanoInk
for different applications. None of these technologies, though, could compete in cost and throughput with the rotating drum of a printing press, and so other companies are looking at ultra-low-cost patterning on roll-to-roll (R2R) substrates.
As mentioned in Tom Cheyney's recent flexible electronics article
sister publication Small Times
, Hewlett-Packard Laboratories (Palo Alto, CA) and PowerFilm Solar (Ames, IA) are working toward large-area arrays of TFTs on 330mm wide polymer substrates using exclusively R2R processes. Ohseung Kwon of HP Labs explained some details of the SAIL process which allows for 100nm feature alignment across a roll moving at >5 meters/min. Prototype work has been done
By encoding the geometry for all of the patterning steps into discrete heights of a 3D masking structure, the SAIL process borrows from the experiences of the MEMS industry in multilayer hardmask integration. All mask-formation is done before any etching, so that alignment is maintained regardless of process induced substrate distortion. Using a 100mm wide polyimide substrate (Kapton brand) for prototyping the UV-curable NIL process, they have achieved 4 imprint levels in 0.5μm step heights.
To form the TFTs, five blanket layers are deposited sequentially to form a stack, with no deposition temperature >260°C: PowerFilm had already developed PECVD
for nitride and oxide as part of a-Si:H PV fab R&D for DARPA. HP Labs contributed their house-built R2R coater. The complex thin-film stack is as follows:
* Al gate metal,
* SiNx dielectric,
* a-Si semiconductor,
* n+ micro-crystalline-Si contact, and
* Cr top metal for source/drain.
Then the SAIL layer is formed, careful resist ashing allow for 3 or 4 layers with unique patterns to be exposed as masks. TFTs with on-off ratio >E7 (with dimensions 40μm × 2μm or 100μm × 1μm) have been printed.
The etching integration with this self-aligned mask is understandable challenging. Most are wet and use home-brew tooling, but some need to be dry plasmas. The wet etch system is 1/3 meter wide and can separate source/drain areas from gate areas at 1.5 meters/min. “If you can achieve the etch undercut very well, everything else can be done in a planar manner,” said Kwon regarding the complex multi-step etch flow.
R2R Plasma etching technology is challenging…to start with there is no “end-point” as commonly considered in wafer etching systems. Transferring the substrate from atmosphere to vacuum is achieved by load-locks for each roll that becomes sort of a batch. These are certainly not continuous processes. “Since we are using this kind of roll, once the surface is rolled up it serves as its own cleanroom,” explained Kwon.—E.K.
Labels: electronics, litho, printed, R2R, roll-to-roll, SAIL, TFUG
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080512: SAIL to fly
Ed’s Threads 070323Musings by Ed Korczynski on March 23, 2007Integration extends 193nm litho
As thoroughly reported by WaferNews, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. Whether dry or with the wafer under immersion (193i) of a fluid to push the resolution, there really is no other choice besides direct-write
. Consequently, process development engineers now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.Double-exposure (in which a single resist stack is exposed twice) and double-patterning (with at least one thin-film hard mask, and usually two exposures)
with 193nm are now in use and under development in different CMOS fabs. Double- and triple-patterning has been used in the MEMS industry for over 20 years, to allow for all lithography to be completed before complex multi-step etching of physical structures such as membranes and cantilevers.
A classic and well-known integration trick to extend litho is “resist-trim.”
Used for gate formation, resist lines defined by lithography are plasma etched to thin them and so achieve linewidths below the resolution of the optics. Various resist-swelling techniques can narrow contact holes below lithographic resolution limits. Applied Materials now claims an anisotropic plasma etch of a hardmask can narrow holes.
Applied Materials now also touts two different hardmask materials: a dielectric advanced patterning film (APF) for most applications, and a 25-30nm thick PVD titanium nitride (TiN) film for integration with low-k dielectrics having porosity of up to 30%. The $2-$3/wafer APF has the amazing ability to “heal” line-edge roughness (LER) from an upper resist layer. Because it is not built out of large molecules like resist, the byproducts of etching the APF are small ligands with sp3 hybrid bonds that coat exposed sidewalls with diamond-like carbon, which preferentially fills in 1-2nm features. Consequently, LER of 2.5 nm in resist becomes just 1.5 nm when etched into the APF.
Applied Materials has developed a complex, self-aligned double-patterning scheme that uses a quadruple-hardmask and a self-aligned spacer nitride with a single litho step:
- Depositing a blanket stack of APF + oxide + APF + nitride on top of poly,
- Coat resist and dry 193nm litho of pattern into resist,
- Trim resist, then etch pattern into nitride and top APF,
- Deposit self-aligned sidewall spacer nitride,
- Etch APF, and then
- Etch poly gate features using remaining spacer nitride.
Improved metrology will certainly be essential to manage any of this new integration. Metrology now controls the process—it doesn’t merely monitor—and it must also provide the vital data to build design and litho models. For example, building an OPC model requires accurate metrology to capture the interdependencies between the mask, resist, and at least one etch. Thus, SPIE now includes thorough sessions on DFM and metrology.
The history of semiconductor manufacturing technology is the history of risk-avoidance at the bleeding-edge of human knowledge. “The industry is overall conservative as any manufacturing industry must be,” commented TI’s Hans Stork in his keynote address at SPIE this year. “We only move to a new material or a new approach if there is no alternative.”
Technologies must hit the sweet spot in the middle of capability/risk/cost, and it’s the overall integrated process that counts. If multiple low-risk and inexpensive process steps can replace a single risky and overall more expensive step, then the reduced cost and risk of the multi-step flow will always be worth the longer fab cycle-time.
Labels: 193, direct write, hardmask, integration, LER, litho
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070323: Integration extends 193nm litho