Ed’s Threads 080324Musings by Ed Korczynski on March 24, 2008
Etching new IC materials at 32 and 22nm
Silicon Valley was once the center of the silicon-based IC manufacturing world, and though IC fabs are now located globally the valley maintains momentum as the center of IC R&D. The North-California Chapter of the American Vacuum Society (NCCAVS) still runs regular users groups on important industry topics
, and the plasma-etch users group (PEUG) meeting on March 13th featured presentations by IBM and Applied Materials on advanced etch processes for 32nm and 22nm node ICs
Nicolas Gani, of the silicon etch division of Applied Materials, presented on work done in collaboration with IBM on plasma etching for gate-stacks for 45nm and 32nm node CMOS transistors. Since the stack is composed of multiple materials, different single-wafer etch chambers for different etch conditions are ideally clustered together into a single tool. One chamber is designed for poly-silicon etching at relatively low temperature, while another chamber is designed for high-k/MG material removal at relatively higher temperatures of 130-220°C.
High-k materials such as HfO2 demonstrate etch rates in Cl2 plasmas with zero bias power that increase linearly by ~4X over the 100-200°C range, though rate-studies indicate there is some ionization component to the etch even without bias. High source-power can actually induce polymerization which shuts down the HfO2 etching. Using 20 W bias allows for 100s Å/min etch rate. One of the key issues in tuning etch processes is the elimination of any “foot” at the bottom cross-section of line-stacks. Applied Materials has shown that etching at >200°C leaves <1nm of a foot, while a 3-4nm foot is seen at <100°C. The temperature control is modest since for etching at greater than ~150°C the reaction is surface limited so that uniformity across the wafer is guaranteed even with an ESC only controlling to ~5°C.
Nicolas Fuller of IBM Research talked about plasma etching challenges for 22nm node etching, with most of the work done at Yorktown Heights, though unit process work was also done at East Fishkill and Albany. Device options for 22nm include finFETs and SOI, and both structures create unique etch challenges. “The fin itself can charge,” explained Fuller. “It may have a hardmask, and charging during the etch can produce an ion steering effect that induces greater etch rate in the middle of structures.” Going to 3D represents a challenge, and—as per the classic wisdom—also an opportunity. “Here charging potentially represents an advantage. You might want to charge the metal gate to induce ion steering to minimize footing,” claimed Fuller.
As complex as today’s leading edge 45nm production may be, halving the scale seems like it could be an order of magnitude more difficult. For sidewall image transfer (SIT) to get the types of structures at 22nm node fin pitches we may need some manner of atomic-level etching (ALE) to conceptually match ALD. New line-edge roughness (LER) and line-width roughness (LWR) issues will be induced by multiple exposures and multiple etches anticipated in 22nm integrated double-patterning process flows.
IBM shows us that after lithography to form 24nm wide lines at 80nm pitch there was 2.6/4.9 LER/LWR (3 sigma); and best lab results were 1.4/2.3 has been achieved with multistage etches of organic/inorganic materials as masks using boutique combinations of e-beam and optical litho. Plasma etch work ongoing at Albany now suggest that high-frequency plasma parameters are the main factors which must be controlled to minimize LER/LWR. There’s barely any CD error budget left, and etch has to share the vanishingly few nanometers with lithography and metrology and deposition. Hold tight.
Labels: 22nm, 32nm, etch, LER, materials research, NCCAVS, PEUG
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080324: Etching new IC materials at 32 and 22nm
Ed’s Threads 070323Musings by Ed Korczynski on March 23, 2007Integration extends 193nm litho
As thoroughly reported by WaferNews, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. Whether dry or with the wafer under immersion (193i) of a fluid to push the resolution, there really is no other choice besides direct-write
. Consequently, process development engineers now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.Double-exposure (in which a single resist stack is exposed twice) and double-patterning (with at least one thin-film hard mask, and usually two exposures)
with 193nm are now in use and under development in different CMOS fabs. Double- and triple-patterning has been used in the MEMS industry for over 20 years, to allow for all lithography to be completed before complex multi-step etching of physical structures such as membranes and cantilevers.
A classic and well-known integration trick to extend litho is “resist-trim.”
Used for gate formation, resist lines defined by lithography are plasma etched to thin them and so achieve linewidths below the resolution of the optics. Various resist-swelling techniques can narrow contact holes below lithographic resolution limits. Applied Materials now claims an anisotropic plasma etch of a hardmask can narrow holes.
Applied Materials now also touts two different hardmask materials: a dielectric advanced patterning film (APF) for most applications, and a 25-30nm thick PVD titanium nitride (TiN) film for integration with low-k dielectrics having porosity of up to 30%. The $2-$3/wafer APF has the amazing ability to “heal” line-edge roughness (LER) from an upper resist layer. Because it is not built out of large molecules like resist, the byproducts of etching the APF are small ligands with sp3 hybrid bonds that coat exposed sidewalls with diamond-like carbon, which preferentially fills in 1-2nm features. Consequently, LER of 2.5 nm in resist becomes just 1.5 nm when etched into the APF.
Applied Materials has developed a complex, self-aligned double-patterning scheme that uses a quadruple-hardmask and a self-aligned spacer nitride with a single litho step:
- Depositing a blanket stack of APF + oxide + APF + nitride on top of poly,
- Coat resist and dry 193nm litho of pattern into resist,
- Trim resist, then etch pattern into nitride and top APF,
- Deposit self-aligned sidewall spacer nitride,
- Etch APF, and then
- Etch poly gate features using remaining spacer nitride.
Improved metrology will certainly be essential to manage any of this new integration. Metrology now controls the process—it doesn’t merely monitor—and it must also provide the vital data to build design and litho models. For example, building an OPC model requires accurate metrology to capture the interdependencies between the mask, resist, and at least one etch. Thus, SPIE now includes thorough sessions on DFM and metrology.
The history of semiconductor manufacturing technology is the history of risk-avoidance at the bleeding-edge of human knowledge. “The industry is overall conservative as any manufacturing industry must be,” commented TI’s Hans Stork in his keynote address at SPIE this year. “We only move to a new material or a new approach if there is no alternative.”
Technologies must hit the sweet spot in the middle of capability/risk/cost, and it’s the overall integrated process that counts. If multiple low-risk and inexpensive process steps can replace a single risky and overall more expensive step, then the reduced cost and risk of the multi-step flow will always be worth the longer fab cycle-time.
Labels: 193, direct write, hardmask, integration, LER, litho
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070323: Integration extends 193nm litho