Ed’s Threads 080324Musings by Ed Korczynski on March 24, 2008
Etching new IC materials at 32 and 22nm
Silicon Valley was once the center of the silicon-based IC manufacturing world, and though IC fabs are now located globally the valley maintains momentum as the center of IC R&D. The North-California Chapter of the American Vacuum Society (NCCAVS) still runs regular users groups on important industry topics
, and the plasma-etch users group (PEUG) meeting on March 13th featured presentations by IBM and Applied Materials on advanced etch processes for 32nm and 22nm node ICs
Nicolas Gani, of the silicon etch division of Applied Materials, presented on work done in collaboration with IBM on plasma etching for gate-stacks for 45nm and 32nm node CMOS transistors. Since the stack is composed of multiple materials, different single-wafer etch chambers for different etch conditions are ideally clustered together into a single tool. One chamber is designed for poly-silicon etching at relatively low temperature, while another chamber is designed for high-k/MG material removal at relatively higher temperatures of 130-220°C.
High-k materials such as HfO2 demonstrate etch rates in Cl2 plasmas with zero bias power that increase linearly by ~4X over the 100-200°C range, though rate-studies indicate there is some ionization component to the etch even without bias. High source-power can actually induce polymerization which shuts down the HfO2 etching. Using 20 W bias allows for 100s Å/min etch rate. One of the key issues in tuning etch processes is the elimination of any “foot” at the bottom cross-section of line-stacks. Applied Materials has shown that etching at >200°C leaves <1nm of a foot, while a 3-4nm foot is seen at <100°C. The temperature control is modest since for etching at greater than ~150°C the reaction is surface limited so that uniformity across the wafer is guaranteed even with an ESC only controlling to ~5°C.
Nicolas Fuller of IBM Research talked about plasma etching challenges for 22nm node etching, with most of the work done at Yorktown Heights, though unit process work was also done at East Fishkill and Albany. Device options for 22nm include finFETs and SOI, and both structures create unique etch challenges. “The fin itself can charge,” explained Fuller. “It may have a hardmask, and charging during the etch can produce an ion steering effect that induces greater etch rate in the middle of structures.” Going to 3D represents a challenge, and—as per the classic wisdom—also an opportunity. “Here charging potentially represents an advantage. You might want to charge the metal gate to induce ion steering to minimize footing,” claimed Fuller.
As complex as today’s leading edge 45nm production may be, halving the scale seems like it could be an order of magnitude more difficult. For sidewall image transfer (SIT) to get the types of structures at 22nm node fin pitches we may need some manner of atomic-level etching (ALE) to conceptually match ALD. New line-edge roughness (LER) and line-width roughness (LWR) issues will be induced by multiple exposures and multiple etches anticipated in 22nm integrated double-patterning process flows.
IBM shows us that after lithography to form 24nm wide lines at 80nm pitch there was 2.6/4.9 LER/LWR (3 sigma); and best lab results were 1.4/2.3 has been achieved with multistage etches of organic/inorganic materials as masks using boutique combinations of e-beam and optical litho. Plasma etch work ongoing at Albany now suggest that high-frequency plasma parameters are the main factors which must be controlled to minimize LER/LWR. There’s barely any CD error budget left, and etch has to share the vanishingly few nanometers with lithography and metrology and deposition. Hold tight.
Labels: 22nm, 32nm, etch, LER, materials research, NCCAVS, PEUG
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080324: Etching new IC materials at 32 and 22nm