Ed’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008
MRS meeting covers nanostuff and microthingsOver 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the semiconductor manufacturing industry at any given time. Theory and results for new IC memory cells, extensions of CMOS logic, and future quantum-dots and nano-rods were shown.
Graphene still seems like a possible replacement for silicon in ICs.
In his
Kavli plenary lecture in nanoscience, Prof. A. Paul Alivisatos of UC-Berkeley described recent work by his group and others on transformations in nanocrystals. Chemical transformations can be used to obtain complex nanocrystalline structures though sequential chemical operations. In an example, CdSe reacted with Ag+ to form Ag2Se which could then be combined with Cd2+ to completely reverse back to CdSe, while the volume of the nanoparticle was completely preserved. Such cation exchanges can occur in semiconductor nanorods and hollow spheres with shape preservation, but when shapes do transform their final forms are currently difficult to predict.
Much of the new materials work is targeted toward finding nanoscale structures which can switch between two measurable states to function as memory cells. Two of the newer random-access memory (RAM) cell types under development are phase-change RAM (PRAM) and resistive RAM (ReRAM).
With Numonyx now officially launched to commercialize PRAM along with Flash, there were many papers looking at manufacturing process flows to optimize the deposition and programming of the
antimony-telluride (SbTe) family of “calcogenide” materials which undergo thermally-assisted transitions between crystalline and amorphous phases. Independent of the MRS meeting,
materials supplier ATMI recently announced co-development plans with Ovonyx for calcogenide CVD precursors.
ReRAM using metal-oxides as switching elements comes in two fundamentally different variations: one-time programmable through the growth of nano-metallic-filaments, and reversible through ionic transport between electrodes. ReRAM materials may be used in PRAM-like cells, or also used as
the switching element in cross-bar architecture arrays. HP Labs, US NIST, and Hokkaido University all showed advances in hybrid circuits built using cross-bar arrays.
For extensions of CMOS logic, with a somewhat clear path forward in new materials for high-k and metal gates, a lot of research now centers on doping technologies. G. Lansbergen et al. (B3.7) from TU Delft (The Netherlands) along with Purdue (USA), University of Melbourne (Australia), IMEC (Belgium), and Caltech (USA) showed the ability to work with a single Arsenic dopant atom in a p-MOS finFET; their experiments represent the first evidence of the ability to engineer the quantum state of a single-donor electron by surface gate control. While single-ion doping is way beyond today’s fab specs, more precise control is needed for the placement of often <100 atoms for channels and contacts.
Wilfried Vandervorst of IMEC showed that
Laser Spike Anneal (LSA) which is essentially “diffusion-less” calls for re-integration from prior rapid-thermal annealing (RTA) schemes where lateral diffusion is significant. Due to the very low thermal budgets needed to form ultra-shallow junctions (USJ), LSA is more subject to pocket dopant fluctuations than spike anneals. Random dopant fluctuations must be controlled, along with structural variations on gate cross-sections which appear as undercuts and footing. LSA helps equivalent oxide thickness (EOT) scaling for gate dielectrics by elimination of a 2-3Å thick re-growth layer. However, to ensure reliability in gate stacks, an RTA step can be added after LSA to improve the situation somewhat. Looking forward to embedded SiGe, LSA so far induces junction leakage and defects gliding along certain crystalline planes which unfortunately relaxes desired strain. LSA for embedded SiC, however, avoids SiC relaxation which improves the strain retention in nMOS. Gate profile control is critical for diffusion-less USJ, which may mean gate-last integation schemes will be easier to integrate.
Karuppanan Sheker, of SemEquip, presented on how to use cluster-carbon implants to improve the Si:C layer formation. There is ~2% limit to how much C can be substituted in silicon lattice. At the
VLSI Technology Symposium 2007, IBM showed [C]sub of 1.65% with mono-atomic C implants and pre-amorphizing implants (PAI). Using clustered carbon eliminates the need for the PAI and provides [C]sub >2%. The source is two benzene rings in the form of C14H14, which upon striking a silicon crystal in the 6-10keV implant energy range automatically induces amorphization with depth of 20nm-40nm. The greater the amorphous layer thickness the higher the percentage C which can be substitutionally incorporated.
Newer finFET architectures, which may first be used for SRAM arrays, require unique integration flows. Mark van Dal, NXP-TSMC Research Center, showed that when implants into fins amorphized the silicon material, the re-crystallization in complex fin shapes results in scattering and other sources of variability. The exact reason for the device degradation is not known, but using either BF2 or B+Ge implants (both of which induce amorphization) result in more transistor variability. At fin widths of 1µm there is no difference, but for fins <0.1µm wide the effect is clearly seen. When non-amorphizing B implants are used, no device performance degradation is observed.
— E.K.
Labels: CMOS, finFET, graphene, materials research, nano, PRAM, ReRAM
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080331: MRS meeting covers nanostuff and microthings
