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080519: Resistive memory resists definition
Ed’s Threads 080519
Musings by Ed Korczynski on May 19, 2008 (updated May 21)

Resistive memory resists definition
My recent blog entry about "memristors" and ReRAMs generated a lot of feedback (both on and off the record). The prevailing opinion seems to be that many companies have been working on resistive memory cells for many years, and most of the complex oxide structures at the core of these devices could function as “memristors” if people chose to look at them as analog circuit elements. Another variation on this complex theme was recently announced with Axon Technologies receiving a US patent for a copper-doped silicon oxide materials-system.

Axon, a spin-out from Arizona State University (ASU), is working with several potential partners on commercialization and full production. Dr. Michael Kozicki, founder and president of Axon, explained the science behind the technology in an exclusive interview with WaferNEWS. The company just announced it has been awarded US Patent # 7,372,065 for using copper and silicon dioxide to form a ReRAM they call a "programmable metallization cell" (PMC) memory device -- the 27th US patent issued to Axon relative to this technology since work started 10 years ago at ASU. Kozicki told WaferNEWS that the company has "strong technical and business relations with several companies in the memory and storage industry," including a license of the PMC technology to Micron and Infineon.

With modest voltages and very low current, you can grow a metallic nano-bridge that dramatically lowers resistance. By using common interconnect materials, the cost of integrating a huge range of low-cost discrete and embedded memory cells can be substantially reduced. “We honestly believe that going this way offers almost free memory for any chip," Kozicki said. "In essence you are adding materials and at most two mask steps in BEOL. So the cost of adding just a few kilobytes to a chip could be marginal.”

After first starting with tungsten-oxide as the electrolyte for main-steam IC applications, Axon found limitations of ~10,000 read-write cycles before breakdown. In contrast, “the first copper-oxide cells we built showed 1M read-write cycles,” Kozicki said. A somewhat porous silicon oxide can work. “If you have a very dense thermally grown oxide then ions move very slowly,” he noted. The company experimented with both CVD and PVD oxide, with the most success with PVD seen so far. “We could potentially expand this to spin-on-glasses too,” he added.

Kozicki explained that the fundamental ion transport speed in the oxide controls the inherent tradeoff between switching-speed and stability. Working with “stable” interconnect materials results in switching speed on the order of micro-seconds or hundreds-of-nanoseconds. Access time is determined by the surrounding circuitry, and so should be comparable to DRAM for reads. Thus, for writing, this should still be comparable to flash memory in terms of speed, but with lower current (since there would be no charge pumps) and maybe one extra mask.

ReRAM—such as Axon’s PMC variant—could replace DRAM for many applications and even some NAND flash due to an area advantage. In addition to all of these possible uses of solid electrolytes as digital memory cells, analog functionality along the lines of a “memristor” is also possible. “A solid electrolyte is simply a glass in which ions easily conduct,” explained Kozicki. “At the highest possible level, the number of things you can do with moving ions around goes way beyond memory.”

“The analog-ness of these devices is not in question,” declared Kozicki, adding that working with Polytechnica Milano has shown "some interesting effects.” Programming 10μA you get on the order of 10kΩ, if you program with 100μA then you’re down to ~1000Ω, and 1μA gives you 100kΩ. “These states are quite stable," he said. “The resistance ends up being what is the aggregate current flowing through the device.”


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080505: When is a Memristor a ReRAM?
Ed’s Threads 080505
Musings by Ed Korczynski on May 5, 2008

When is a Memristor a ReRAM?
HP published that they are the first to have fabricated a novel circuit element first predicted in 1971 called the “memristor.” The HP authors claim that, “until now no one has presented either a useful physical model or an example of a memristor.” HP is certainly leading the world, but as one of many companies working on this technology for resistance-change random-access memory (ReRAM) applications. This spring’s Materials Research Society meeting featured an afternoon session on ReRAM with presentations by HP as well as Fujitsu, FZ Jülich, IMEC, Panasonic, and Samsung.

Antique circuit theories are rarely invoked at MRS meetings, so the focus of the ReRAM session was all about how you engineer complex atomic-layer oxide elements. Another sub-session covered organic switching elements for printable ultra-dense memories in the far future. In other memory technology, the usual suspects are still doing the same tap-dances about FeRAM and MRAM, but PRAM seems to have new momentum due to investments by Intel and ST in Numonyx and so may take over some of the mainstream.

Robert Muller of IMEC presented fundamentals of ReRAM cells based on Cu+ and Ag+ charge-transfer complexes for memory applications. Using Ag/CuTCNQ/Al structures, Cu+TCNQ- is a solid ionic conductor, and so a potential can reduce alumina to aluminum along with a corresponding oxidation of the “noble” metal on the other side. The main resistance change is expected as an interfacial effect within a few nm gap between the solid ionic conductor and the aluminum electrode, where Cu filaments form as conductors. IMEC has seen retention time of up to 60 hours so far, but theoretically this can be much higher. The integration problem is that TCNQ begins to degrade at 200°C, so another material may be needed for dense IC memories.

Z. Wei et al. of Panasonic talked about FeOx ReRAM, as first presented by S. Muraoka et al. at IEDM 2007. Fe3O4 reduces to higher-resistance Fe2O3. Both bipolar and unipolar transitions are possible, however, the bipolar high-resistance state (HRS) degrades in only ~100 hours at 85°C, while the unipolar transition retains high resistance to >1000 hours. Interestingly, the low-resistance state (LRS) of the unipolar mode shows metallic (instead of semiconducting) dependence of resistivity to temperature. Both fast switching and long retention may be achieved by combining bipolar (<100ns>1000 hours @85°C) modes.

Herbert Schroeder et al. of Jülich Forshlungszentrum (“FZ Jülich”) showed a simple stack geometry using 100nm thick Pt top and bottom electrodes with a central TiO2 layer 27-250nm thick. As produced, Pt/TiO2/Pt is insulating (in the MΩ to GΩ range) so that “electroforming” is needed. Up to 30mA is needed for the reset current with simple unipolar stacks, though HRS/LRS is ~1000 which is excellent and has been shown with read-out voltages of 0.3V over up to 80 cycles. Bipolar switching has a HRS/LRS of only ~5, but the reset current is merely 1mA and so applicable to real-world circuits. Room-temperature reactive sputtering of Ti results in polycrystalline TiO2 with columnar grains of 5-20nm dia. The possible mechanism of “forming” is the electro-reduction of TiO2 into TiO or Ti which creates oxygen ions to drift to the anode and appear as voids.

H. Kawano et al. of Fujitsu Labs (along with the Nagoya Institute of Technology) explained some of the inherent trade-offs in device properties depending upon the top electrode used with Pr0.7Ca0.3MnO3 bipolar switching material. The mechanism for bipolar switching is more complex and the switching speed strongly depends on the electrode material; using Ag or Au as the top electrode results in 100-150ns, while an easily oxidized metal such as Al or Ti results in ~1ms. Ta forms a thinner oxide which allows 100ns switching with HRS:LRS of 10 at 7V, and this ratio was maintained up to 10,000 cycles. With Pt as both electrodes they saw no ReRAM effects.

Julien Borghetti of HP Information and Quantum System Lab (IQSL) said that they use a TiO2 target to sputter ~30nm TiOx and after a forming step the HRS:LRS ratio is 1000-10,000 for bipolar switching. After formation, the HRS shows essentially no temperature dependence on the conduction, which implies that tunneling current must be responsible for the conduction. From IV curves at different temperatures and biases, it seems that most of the TiOx has parallel degenerate or metallic states which account for ~200Ω resistance which is present in both the HRS and LRS. Then there is a tunneling gap which accounts for the difference between the two states, and it seems to be <3 nm thick and consists of some defects which assist in the tunneling. Cryogenic tests down to 3°K show resonant tunneling through a degenerate gas of electrons.

More details on the HP ReRAM manufacturing process can be found in my recent SST article, “Imprint litho forms arrays for new fault-tolerant nanoscale circuits” (Solid State Technology, April 2008) which summarizes the main information the company has presented at IEDM, SPIE, and MRS conferences in the last half-year. HP has shown how cross-bar circuits built with ReRAM switches can function both as interconnects and as logic elements. The titania/platinum materials set which can provide reversible ReRAM is not ready for production, but alumina/aluminum is ready to go and can provide irreversible effects. HP Corvalis in Oregon, with its old subtractive Al metal fab, has all the processing capability needed to integrate alumina/aluminum ReRAM with traditional CMOS circuitry for FPGA applications.

Does calling the fundamental switching element in a ReRAM a “memristor” make it switch any faster or retain a state any longer? HP’s labs and fabs do great work and deserve recognition, but unless HP plans to use memristors as novel circuit elements it’s confusing to use the term for ReRAM memory arrays. One blogging circuit designer has already imaged the possibility of building large-scale analog neural networks out of memristor arrays. Now that we’ve discovered that our ReRAMs could be memristors, the next question is: what do we do with them?


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Anonymous Anonymous said...

Maybe Stan (now a Bay Area radio star) should have read reference 4 in his own paper. It contains stuff like, oh, results and facts on a whole bunch of devices that walk and quack like "memristors". Other references in his paper and the Nature Materials review suggest that there are also previous models that allowed some fairly sophisticated circuit design. So, what did HP "invent", like, exactly? I think this big PR over-the-top-fest will come back to haunt the good Dr. Williams and his otherwise competent team.

Tue May 06, 11:01:00 PM PDT  
Anonymous Tarun Kansal said...

ReRAM seems to be a grear technology for future. But I m wondering what are its advantages comparing to our ongoing memory technologies??

Wed May 07, 01:15:00 AM PDT  
Blogger SST's Ed's Threads said...

In response to the comment by "anonymous," I can only say that I suspect that this PR is part of “building the new blueprint for corporate research” as directed by new HP Labs head Prith Banerjee, to convert “scientific discoveries into the marketplace.”

Wed May 07, 01:03:00 PM PDT  
Anonymous Anonymous said...

Memristor is NOT ReRAM. Typically a resistance-change memory device changes its state only above a certain threshold voltage. However, according to the equations of memristor in HP's paper, the memristance M is a function of q, which is the integral of idt. So applying low voltage is also gradually changing the state, and the resistance state should be continuous.

Wed May 07, 01:29:00 PM PDT  
Blogger SST's Ed's Threads said...

A memristor may technically never "be" a ReRAM, yet essentially identical engineered materials are used for both devices. Theoretically an analog memristor should indeed demonstrate continuous change in resistance, while a ReRAM is intended to store digital information as two or more discrete resistance levels. The control circuitry must be completely different between the two, yet the engineered oxide which changes resistance may be identical.

Wed May 07, 03:41:00 PM PDT  
Anonymous Anonymous said...

Hello anonymous - hey, same name as me (maybe we even work for the same Higher Power). The threshold thing may be a bit of a red herring as the key to memristor action is "history dependent resistance" and all of the other referenced devices possess this. But you do bring up a very good point - how can you build a memory cell, let alone an array of them, if you are using a device that does not have some kind of threshold voltage? A threshold-less device would not be a memory cell, more of a read-disturbistor. In any case, the "real" TiO2 device shown in the HP paper does have a threshold (somewhere between 0.5 and 1 volt). So I ask again, what exactly did HP invent here? A really bad memory cell or a device that has been in the literature for decades?

Wed May 07, 09:44:00 PM PDT  
Blogger SST's Ed's Threads said...

Think of it this way: how can a capacitor be the memory element of a DRAM cell? In the same manner a memristor can be the memory element in a ReRAM cell (only the capacitor leaks and so is volatile, while the memristor retains resistance and so is non-volatile). ReRAM uses the voltage-induced switching effect between high- and low-resistance states, which can be read as the 1s and 0s of digital memory.

Thu May 08, 01:11:00 PM PDT  
Blogger Marcelo said...

I found it quite unfortunate
that S. Williams et al. in their recent Nature paper have simply ignored our recent work in theoretical modeling of
the non-volatile resistive switching effect in MIM structures that use transition metal oxide dielectrics.

Our first work appeared in 2004 in Physical Review Letters, and subsequent work appeared in PRL and APL.

Contrary to their claim in the opening paragraph of the Nature paper
"... until now no one has presented either a useful physical model or
an example of a memristor.", our 2004 paper does introduce a model,
which certainly seems to have been useful as demonstrated by the over 100 citations it has received so far.

M. J. Rozenberg, I. H. Inoue and M. J. Sanchez, Phys. Rev. Lett. 92, 178302 (2004).

M. Rozenberg
[email protected]

Sat May 10, 04:14:00 AM PDT  
Anonymous Krieger said...

First of all I would like to remind that to the moment of publication of L. Chaua’s paper a lot of papers about switching resistance of thin oxide as well organic films were already published. (Discussion of L. Chaua’s paper is separate story).
It was suggested many mechanism of switching and mechanism memory in thin films. By this time are published about 1000 papers about switching and memory phenomena in different types of thin films and theoretical papers explained there phenomena.

According L. Chaua’s definition a memrestor is charge- controlled device, its resistance (conductance dependents of the complete past story (injected charges (g) or integral of memristor current).

Resiatance of HP’s device is determined by changing distribution of charges (oxygen vacancies – oxygen ions) within TiOx film. By program, one part of the TiOx film receives oxygen ions (TiOx film is doped by oxygen ions) other part of the TiOx film loses oxygen ions (TiOx film is undoped). The balance of a charge in HP’s memristor cell does not change. It is necessary to distinguish a flow of electron charges and flow of oxygen ion charges through cell. Only ionic charges can change memristor resistance.

I agree with Anonymous, Memristor is not ReRAM. HP’s memristor don’t have threshold voltage. It is mean memristor cell can be program or erased by read voltage.
Basically, it is possible to use memristor as memory cell, but reading is destructive, like DRAM. It is mean after every reading (pulse at least after every 100 or 1000 reading pulse it is necessary again reprogram the memristor cell without threshold voltage.

There are a lot of resistance memory cells which have threshold voltage and use doped and undoed phenomena in thin films (conjugated polymer and related organic materials, inclusion compounds like WO3 and semiconductor). These memory cells use additional superionic layer as source of different type of ions. (See for example Spansion and AMD patents. There are about 30 patents).

From point of view circuit designer, it is more useful and simple do use switchable diode with memory which also have threshold voltage and use doped and undoed phenomena in thin films. (See for example Spansion and AMD patents).

Switchable diodes with memory allow ease to create a passive memory array without additional diode (in this case with the memristor cell, it is desirable to use Zener diode).
I guess, switchable diode with memory can be called as “memdiode”. It is joke.

Sun May 18, 09:28:00 PM PDT  
Anonymous Anonymous said...

The HP result uses Pt/TiO2/Pt which has been used as a ReRAM or RRAM. The big question is when they apply 1 Volt across a 5 nm layer, that gives a 2 MV/cm electric field. Probably the less conductive part has even higher electric field. Why doesn't the layer breakdown under this condition?

Tue May 20, 11:39:00 PM PDT  
Anonymous Anonymous said...

Krieger (mein Bruder): HP gets around the destructive read problem by using Alternating Current.

Tue Jun 10, 11:49:00 AM PDT  

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080331: MRS meeting covers nanostuff and microthings
Ed’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008

MRS meeting covers nanostuff and microthings
Over 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the semiconductor manufacturing industry at any given time. Theory and results for new IC memory cells, extensions of CMOS logic, and future quantum-dots and nano-rods were shown. Graphene still seems like a possible replacement for silicon in ICs.

In his Kavli plenary lecture in nanoscience, Prof. A. Paul Alivisatos of UC-Berkeley described recent work by his group and others on transformations in nanocrystals. Chemical transformations can be used to obtain complex nanocrystalline structures though sequential chemical operations. In an example, CdSe reacted with Ag+ to form Ag2Se which could then be combined with Cd2+ to completely reverse back to CdSe, while the volume of the nanoparticle was completely preserved. Such cation exchanges can occur in semiconductor nanorods and hollow spheres with shape preservation, but when shapes do transform their final forms are currently difficult to predict.

Much of the new materials work is targeted toward finding nanoscale structures which can switch between two measurable states to function as memory cells. Two of the newer random-access memory (RAM) cell types under development are phase-change RAM (PRAM) and resistive RAM (ReRAM). With Numonyx now officially launched to commercialize PRAM along with Flash, there were many papers looking at manufacturing process flows to optimize the deposition and programming of the antimony-telluride (SbTe) family of “calcogenide” materials which undergo thermally-assisted transitions between crystalline and amorphous phases. Independent of the MRS meeting, materials supplier ATMI recently announced co-development plans with Ovonyx for calcogenide CVD precursors.

ReRAM using metal-oxides as switching elements comes in two fundamentally different variations: one-time programmable through the growth of nano-metallic-filaments, and reversible through ionic transport between electrodes. ReRAM materials may be used in PRAM-like cells, or also used as the switching element in cross-bar architecture arrays. HP Labs, US NIST, and Hokkaido University all showed advances in hybrid circuits built using cross-bar arrays.

For extensions of CMOS logic, with a somewhat clear path forward in new materials for high-k and metal gates, a lot of research now centers on doping technologies. G. Lansbergen et al. (B3.7) from TU Delft (The Netherlands) along with Purdue (USA), University of Melbourne (Australia), IMEC (Belgium), and Caltech (USA) showed the ability to work with a single Arsenic dopant atom in a p-MOS finFET; their experiments represent the first evidence of the ability to engineer the quantum state of a single-donor electron by surface gate control. While single-ion doping is way beyond today’s fab specs, more precise control is needed for the placement of often <100 atoms for channels and contacts.

Wilfried Vandervorst of IMEC showed that Laser Spike Anneal (LSA) which is essentially “diffusion-less” calls for re-integration from prior rapid-thermal annealing (RTA) schemes where lateral diffusion is significant. Due to the very low thermal budgets needed to form ultra-shallow junctions (USJ), LSA is more subject to pocket dopant fluctuations than spike anneals. Random dopant fluctuations must be controlled, along with structural variations on gate cross-sections which appear as undercuts and footing. LSA helps equivalent oxide thickness (EOT) scaling for gate dielectrics by elimination of a 2-3Å thick re-growth layer. However, to ensure reliability in gate stacks, an RTA step can be added after LSA to improve the situation somewhat. Looking forward to embedded SiGe, LSA so far induces junction leakage and defects gliding along certain crystalline planes which unfortunately relaxes desired strain. LSA for embedded SiC, however, avoids SiC relaxation which improves the strain retention in nMOS. Gate profile control is critical for diffusion-less USJ, which may mean gate-last integation schemes will be easier to integrate.

Karuppanan Sheker, of SemEquip, presented on how to use cluster-carbon implants to improve the Si:C layer formation. There is ~2% limit to how much C can be substituted in silicon lattice. At the VLSI Technology Symposium 2007, IBM showed [C]sub of 1.65% with mono-atomic C implants and pre-amorphizing implants (PAI). Using clustered carbon eliminates the need for the PAI and provides [C]sub >2%. The source is two benzene rings in the form of C14H14, which upon striking a silicon crystal in the 6-10keV implant energy range automatically induces amorphization with depth of 20nm-40nm. The greater the amorphous layer thickness the higher the percentage C which can be substitutionally incorporated.

Newer finFET architectures, which may first be used for SRAM arrays, require unique integration flows. Mark van Dal, NXP-TSMC Research Center, showed that when implants into fins amorphized the silicon material, the re-crystallization in complex fin shapes results in scattering and other sources of variability. The exact reason for the device degradation is not known, but using either BF2 or B+Ge implants (both of which induce amorphization) result in more transistor variability. At fin widths of 1µm there is no difference, but for fins <0.1µm wide the effect is clearly seen. When non-amorphizing B implants are used, no device performance degradation is observed.

— E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.