Ed’s Threads 080505
Musings by Ed Korczynski on May 5, 2008
When is a Memristor a ReRAM?
HP published that they are the first to have fabricated
a novel circuit element first predicted in 1971 called the “memristor.” The HP authors claim that, “until now no one has presented either a useful physical model or an example of a memristor.” HP is certainly leading the world, but as one of many companies working on this technology for resistance-change random-access memory (ReRAM) applications. This spring’s Materials Research Society meeting featured
an afternoon session on ReRAM with presentations by HP as well as Fujitsu, FZ Jülich, IMEC, Panasonic, and Samsung.
Antique circuit theories are rarely invoked at MRS meetings, so the focus of the ReRAM session was all about how you engineer complex atomic-layer oxide elements. Another sub-session covered organic switching elements for printable ultra-dense memories in the far future. In other memory technology, the usual suspects are still doing the same tap-dances about FeRAM and MRAM, but
PRAM seems to have new momentum due to
investments by Intel and ST in Numonyx and so may take over some of the mainstream.
Robert Muller of IMEC presented fundamentals of ReRAM cells based on Cu+ and Ag+ charge-transfer complexes for memory applications. Using Ag/CuTCNQ/Al structures, Cu+TCNQ- is a solid ionic conductor, and so a potential can reduce alumina to aluminum along with a corresponding oxidation of the “noble” metal on the other side. The main resistance change is expected as an interfacial effect within a few nm gap between the solid ionic conductor and the aluminum electrode, where Cu filaments form as conductors. IMEC has seen retention time of up to 60 hours so far, but theoretically this can be much higher. The integration problem is that TCNQ begins to degrade at 200°C, so another material may be needed for dense IC memories.
Z. Wei et al. of Panasonic talked about FeOx ReRAM, as first presented by S. Muraoka et al. at IEDM 2007. Fe3O4 reduces to higher-resistance Fe2O3. Both bipolar and unipolar transitions are possible, however, the bipolar high-resistance state (HRS) degrades in only ~100 hours at 85°C, while the unipolar transition retains high resistance to >1000 hours. Interestingly, the low-resistance state (LRS) of the unipolar mode shows metallic (instead of semiconducting) dependence of resistivity to temperature. Both fast switching and long retention may be achieved by combining bipolar (<100ns>1000 hours @85°C) modes.
Herbert Schroeder et al. of Jülich Forshlungszentrum (“FZ Jülich”) showed a simple stack geometry using 100nm thick Pt top and bottom electrodes with a central TiO2 layer 27-250nm thick. As produced, Pt/TiO2/Pt is insulating (in the MΩ to GΩ range) so that “electroforming” is needed. Up to 30mA is needed for the reset current with simple unipolar stacks, though HRS/LRS is ~1000 which is excellent and has been shown with read-out voltages of 0.3V over up to 80 cycles. Bipolar switching has a HRS/LRS of only ~5, but the reset current is merely 1mA and so applicable to real-world circuits. Room-temperature reactive sputtering of Ti results in polycrystalline TiO2 with columnar grains of 5-20nm dia. The possible mechanism of “forming” is the electro-reduction of TiO2 into TiO or Ti which creates oxygen ions to drift to the anode and appear as voids.
H. Kawano et al. of Fujitsu Labs (along with the Nagoya Institute of Technology) explained some of the inherent trade-offs in device properties depending upon the top electrode used with Pr0.7Ca0.3MnO3 bipolar switching material. The mechanism for bipolar switching is more complex and the switching speed strongly depends on the electrode material; using Ag or Au as the top electrode results in 100-150ns, while an easily oxidized metal such as Al or Ti results in ~1ms. Ta forms a thinner oxide which allows 100ns switching with HRS:LRS of 10 at 7V, and this ratio was maintained up to 10,000 cycles. With Pt as both electrodes they saw no ReRAM effects.
Julien Borghetti of HP Information and Quantum System Lab (IQSL) said that they use a TiO2 target to sputter ~30nm TiOx and after a forming step the HRS:LRS ratio is 1000-10,000 for bipolar switching. After formation, the HRS shows essentially no temperature dependence on the conduction, which implies that tunneling current must be responsible for the conduction. From IV curves at different temperatures and biases, it seems that most of the TiOx has parallel degenerate or metallic states which account for ~200Ω resistance which is present in both the HRS and LRS. Then there is a tunneling gap which accounts for the difference between the two states, and it seems to be <3 nm thick and consists of some defects which assist in the tunneling. Cryogenic tests down to 3°K show resonant tunneling through a degenerate gas of electrons.
More details on the HP ReRAM manufacturing process can be found in my recent SST article,
“Imprint litho forms arrays for new fault-tolerant nanoscale circuits” (Solid State Technology, April 2008) which summarizes the main information the company has presented at IEDM, SPIE, and MRS conferences in the last half-year. HP has shown how cross-bar circuits built with ReRAM switches can function both as interconnects and as logic elements. The titania/platinum materials set which can provide reversible ReRAM is not ready for production, but alumina/aluminum is ready to go and can provide irreversible effects. HP Corvalis in Oregon, with its old subtractive Al metal fab, has all the processing capability needed to integrate alumina/aluminum ReRAM with traditional CMOS circuitry for FPGA applications.
Does calling the fundamental switching element in a ReRAM a “memristor” make it switch any faster or retain a state any longer? HP’s labs and fabs do great work and deserve recognition, but unless HP plans to use memristors as novel circuit elements it’s confusing to use the term for ReRAM memory arrays. One blogging circuit designer has already
imaged the possibility of building large-scale analog neural networks out of memristor arrays. Now that we’ve discovered that our ReRAMs could be memristors, the next question is: what do we do with them?
—E.K.
Labels: FRAM, memory, memristor, MRAM, MRS, PRAM, ReRAM, semiconductor
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080505: When is a Memristor a ReRAM?
Ed’s Threads 080407
Musings by Ed Korczynski on April 7, 2008CNT and graphene dreams may be realCarbon nano-tubes (CNT) are the only viable (pun-intended) new materials being developed to replace copper as the electrical interconnects for future ICs. There are no known room-temperature superconductors, and optical interconnects require relatively slow and expensive lasers and detectors, and CNTs are the future.
The theory and practice of growing CNTs was thoroughly reviewed at this spring’s Materials Research Society (MRS) meeting, and the applications as electronic IC interconnects will be seen at the International Interconnect Technology Conference (IITC) to be held in Burlingame, California in June.
The deadline for submitting late news to IITC is this Friday.
Carbon can form an amazing variety of stable crystals and molecules based on different bond energies and angles between atoms. In crystalline form,
sp2 electron orbitals can form 2D planes of graphite or sp3 electron orbitals can form 3D tetrahedral of diamond. The 2D form of solid carbon shows very interesting properties when reduced down to less than a few atomic layers.
Graphene is one or two atomic layers only, which results in geometrically induced electron energy-band modification and the ability to form semiconducting devices.
Graphene is a great potential “long-shot” technology first reported in January 2006 Solid State Technology…sure to generate many Ph.D. theses and likely to benefit DARPA programs…but still quite a way away from proven as commercially manufacturable.
As Gordon Moore reminds us in this recent interview, “The actual idea of an MOS transistor was patented in the mid-'20s,” though it was not until over 40 years later that Intel started making a business out of it.
Take 60 carbon atoms and you can coax them together into a cage-like spheroid called a “buckyball” or fullerene (C60)—initially predicted by
R. Buckminster Fuller based on the potential for stable bond-angles in regular polyhedra—which has the same 2D form as graphene.
Larger and more complex carbon cage molecules can be formed, and seem to be formed naturally by stars in space. Take a continuous supply of carbon atoms and you can coax them together using a catalyst particle into growing as a nano-tube with that same basic 2D form. You can grow both single-walled CNT (SWCNT) and multi-walled CNT (MWCNT). Both grow off of metal catalyst particles, which must somehow first be deposited in the bottom of vias to form interconnects between lines; making the connection on the top side seems like it will be inherently a bit tricky.
At IITC this year, researchers from MIRAI-Selete and Waseda University (Japan) will show actual integration results for CNT in 160nm diameter vias at temperatures as low as 365°C. The team will report that the CNT fabrication process didn’t degrade a fragile low-
k (2.6) dielectric and that the vias sustained a current density as high as 5.0 MA/cm2 at 105°C for 100 hours with no deterioration.
SEM cross-sections of 160nm-diameter CNT vias fabricated with growth temperatures of (a) 450°C and (b) 400°C (IITC2008 Paper #12.4, “Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current,” A. Kawabata et al.)
One of the reasons that MRS meetings are exciting for materials scientists and engineers is that truly leading results are shown. Oleg Kuznetsov et al.—from Honda Research Institute in Columbus OH (USA) and Goteborg University (Sweden) and Duke University (USA)—presented information on the size-dependence peculiarities of small catalyst clusters and their effect on SWCNT growth. Though exact mechanisms are not fully understood yet, we know that nano-scale catalysts particles play key roles in growth, and that sizes alter growth properties. The general background assumption is a vapor-liquid-solid (VLS) model for growth: carbon in the vapor phase is absorbed into the catalyst particle as a liquid from which solid SWCNT grows out. An observed ‘paradox’ is that with decrease of catalyst size from 3nm to 1nm the required minimum temperature for SWCNT growth increases. Molecular dynamics simulations revealed that reducing the catalyst particle size reduces its solubility of carbon atoms and thereby requires higher temperature for SWCNT growth.
Since the researchers used Fe as the catalyst for SWCNT growth, their rigorous modeling work included a re-working of the classic Fe-C phase diagram where they showed that SWCNTs grow in a liquidous region above the Eutectic point. The Fe-C phase diagram is arguably the foundation of modern materials engineering, since it shows how to make the varieties of steel which are the physical backbone of construction in our age, and is taught in all undergraduate materials science courses. While I haven’t been looking very hard, but this is the first time I’ve seen something new in a Fe-C phase diagram since I left MIT in 1984.
—E.K.
Labels: CNT, graphene, IITC, interconnect, MRS, through-silicon via
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080407: CNT and graphene dreams may be real
