Ed’s Threads 060929Musings by Ed Korczynski on 29 September 2006
Common Platform constellation rolls through town
The “Common Platform Alliance” (CPA) of IBM, Chartered, Samsung, and Infineon gathered to gather customers at the Chartered Technology Forum, Sept. 28, at the Santa Clara Convention Center. The CPA is a complex constellation of companies orbiting IBM in East Fishkill, NY (the single ugliest city name in North America). The CPA would like you to know that 45nm chip production is not for the meek or faint-of-heart, but it you have a 45nm design and don’t already know where you’ll get it fabbed, then you should look them up. You’ll also want to talk to quite a few of their design-for-manufacturing (DFM) software partners -- Blaze DFM’s work to automatically tweak gate-widths to optimize overall chip electrical leakage for Qualcomm was featured in this SST article
It’s Chartered’s show, but the membership in the CPA is a “4 Musketeers” sort of thing: it’s all for one and one for all, all the time. Thus, IBM and Samsung show up too, and everyone openly discusses collaboration and even some competition. They collaborate on technology requirements and development, design automation, and manufacturing fundamentals. They compete for the same customers based on who has the closest prior relationships, and the more valuable special IP for the specific chip/product requirements -- a customer may need special analog or other circuitry, or special final packaging, for example. Dr. Hokyu Kang, VP of advanced technology development for Samsung Electronics, explained during a press conference that, “we use a ‘background information’ list that each company provides to keep track of how much process and manufacturing IP each company brings to the JDA.”
They seem to walk the talk on all levels. In keeping with the spirit of collaboration, marketing folks from all four companies coordinated meetings and event throughout the day at the Chartered event. Multiple outsourced marketing communications companies also worked behind the scenes to keep things running smoothly.
All of the efforts are devoted to attracting and keeping the shrinking number of big fabless companies, such as Qualcomm, NVidia, and Microsoft. There will certainly be fewer companies designing fewer chips at 65nm and 45nm nodes, and >$1M mask sets and tens of millions of dollars in design costs limit design starts. “Some of the low-volume products that are around today will not exist in these newer nodes. Either their functionality will be directly integrated into another chip, or programmability will allow comparable functionality within a single chip,” explained Franz Neppl, Infineon’s SVP of base technologies and services. “That is one way to address time-to-market and design-cost issues.”
With high levels of FUD (Fear, Uncertainly, and Doubt) associated with IC production at these nodes, the CPA positions itself as the least risky way to get a concept into working silicon. Not sure how to port old IP blocks to the newest nodes? Resources are available. Need help with system integration options? That can be provided. Interested in advanced packages for your chips? Amkor has joined the CPA
, too. Not sure what your design-fab tradeoffs may be? Experts will talk to you for a price. You may need to look at circuit layout constraints -- such as orientation with respect to the silicon crystal, or forbidden pitches -- to gain yield in manufacturing. The FUD is based on reality, and any fabless company must make a huge financial bet in starting a new 65nm chip design. Step right up and place your bets; with enough players the house always wins.
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060929: Common Platform constellation rolls through town