Ed’s Threads 061110
Wafer-level packaging in the 3D present
Wafer-level packaging (WLP) may finally reach the mainstream for ICs, according to industry vendors and analysts at the
3rd annual International Wafer-Level Packaging Conference held Nov. 1-3 in San Jose. Among the many presentations on WLP, packaging leader Amkor showed that this technology will soon be applicable to ~85% of all ICs by unit volume, and should see market growth of 25% CAGR over the next five years. Analysts presented details of the markets and applications driving this slow revolution in mainstream packaging.
In recent years, WLP has been applied to relatively small chips with <20 pins. However, larger chips tended to have mechanical reliability problems associated with the differences in thermal expansion coefficients between silicon ICs and the PCBs to which they mount. Now, new WLP technologies coming online early next year should allow for reliable WLP of up to 100-pin devices without underfill.
WLP can be attractive due to both area and cost. Since most WLP is also chip-scale, where the “die is the package,” the package can’t really get any smaller in 2D. Amkor showed that the final package size for a 7x7mm die with 208 I/O pins can be reduced >93% from that needed for a PQFP. The company also says that the price can now “be very competitive” with traditional package types, so the 2D area savings is probably the greatest advantage. Many cell phones and portable game players already incorporate WLP chips, following the lead set by Casio and Amkor to develop WLP for watches in 2004. Tessera’s ShellCase process for cell phone camera chips is also WLP.
Beyond 2D considerations, the world is now actively developing technologies to allow for 3D packaging using through-silicon vias (TSV).
Samsung has shown samples of an eight-layer stacked package, and is working on a 16-layer version. Fraunhofer-IZM continues to lead the world in basic research into WLP and TSV concepts.
Both organizations are part of a new 3D packaging consortium, the semiconductor
Equipment and Materials Consortium for 3D (“EMC-3D”), founded to further TSV for 3D stacking of chips in packages, by developing processes for creating 5-30µm diameter vias through 50µm thinned 300mm diameter wafers using both via-first and via-last techniques. Major processes being integrated include via etch and laser drill, insulator/barrier/seed deposition, micro-via patterning with RDL capabilities, high aspect ratio copper plating, carrier bonding, sequential wafer thinning, backside insulator/barrier/seed deposition, backside lithography, backside contact metal plating, chip-to-wafer placement and attach, and dicing. The cost of ownership (COO) goal for the integrated 3D process is $200/wafer.
EMC-3D founding member Semitool explains that each customers’ copper electroplating process to fill the TSVs is relatively unique. With diameters of 5-30µm and depths 10-50µm for different customers, there is no one generic process that can cost-effectively fill all possible vias without seams or voids.
Once TSVs are formed and wafers are thinned, the actual
stacking may occur at either the chip- instead of wafer-level. 3D WLP requires near perfect yield of all chips on all wafers to ensure decent final yield, while chip-level stacking allows pick-and-place tools to work with normally yielding wafers. Singulation into individual chips may be performed with a dicing saw, laser cutting, or plasma-etching through a mask. Laser-cutting and etching may be relatively affordable if the final silicon wafers are thinned to ≤50µm, and may provide some flexibility in process integration.
WLP -- whether featuring TSVs or not -- is finally moving into the mainstream for chips. No longer just for small chips with few I/Os, WLP is now being used for dense memory stacks, integrating sensors with logic, and general system-in-package (SiP) designs.
—
E.K.
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061110: Wafer-level packaging in the 3D present
