• Ed’s Threads
  Musings by Ed Korczynski on December 15, 2006
  
  Infineon fancies 45nm finFETs
  Based on the presentations at the IEEE International Electron Devices meeting (IEDM) 2006 last week, my prior Ed’s Threads entry concluded with the sentence, “Fins function for both CMOS logic transistors and floating-body memory cells, but they still aren’t likely to be seen before the 32nm node.” Confirming this assessment, representatives from AMD, IBM, Intel, and TI participating in a Tuesday night panel discussion sponsored by Applied Materials all agreed that finFETs will not be needed and therefore not used before the 32nm node.
  
  Dr. Klaus Schruefer, Principal Scientist for CMOS Devices of Infineon Technologies, has a different perspective. In an exclusive telephone interview with SST and WaferNews today, he explained that for 45nm low-standby power (LSTP) SoC applications, finFETs provide equivalent performance to planar transistors with 1/10th the leakage current. Work was done at IMEC and Infineon on “spacer defined fins” to relax the lithography while doubling the fin pitch. The costs of manufacturing are nearly identical, and these chips should consume one-half the battery power.
  
  Infineon has the system-level perspective to think about the pros and cons of different transistor architectures for SoC designs. “What is most important is not to demonstrate this on a single device, but to do it on a circuit level,” explained Schruefer. “Our products are based on SoC, so analog, RF, digital, I/O, and all modules will work based on a system-on-chip integration.” Infineon has shown logic and memory finFETs in the past, and they plan to show RF finFET circuitry as part of a full chip SoC at the VLSI Symposium 2007.
  
  Comparing relative processing complexity of finFETs to 45nm “planar” transistors, the use of raised source/drain regions, selective epitaxy, and complex STI have already made devices not-so-planar. However, Infineon found finFETs to be within 2-3% of planar in terms of overall process complexity. “Going down the road I think it’s a wash,” said Schruefer.
  
  Among the inherent advantages of fins compared to planar FETs: there are no latch-up concerns, no well implants, and no N+-to-P+ spacing concerns, so the circuit can be tightened. “We have our own test structures and our own methodology, and for analog we see a huge improvement in the intrinsic gain,” said Schruefer. “With the right dielectric and the right fin thickness you can really achieve the theoretical performance limits.” Infineon has worked with hafnium-based high-k dielectrics and fin thicknesses ~2/3 of gate length.
  
  The lower the drain-induced barrier lowering (DIBL) the better the circuit performance, and fin structures have 4 to 5 times lower DIBL. “Today, a bulk planar device has a DIBL of ~200 mV/V for a 40nm gate length, while we measure between 30 and 40 mV/V on our devices and it’s very stable,” informed Schruefer. “The linear currents are very important for all circuits today. Even for digital ‘stacked circuits’ with NAND and NOR, it’s not the on currents that are important but the linear current.”
  
  Though dual metal gates are not yet ready for high performance transistors, LSTP transistors can get by with a single in-between metal for both gates, especially if the metal is thinned to control the effective work function (EWF). With improved LSTP circuit performance at the same cost at 45nm, finFETs will certainly be used at 32nm and beyond. When dual metal gates are ready, they may be used with either planar or fin structures. “The basic message with this new device architecture,” stated Schruefer, “is that it really opens up the possibility of going further down the road.”
  
  —E.K.

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