Ed’s Threads 070226

Musings by Ed Korczynski on February 26, 2007

SPIE keynotes dismiss EUV

The organizing committee of SPIE Advanced Lithography -- the conference formerly known as “Microlithography” -- probably didn’t plan for the keynote addresses (Monday Feb. 26) to dismiss EUV lithography, but that’s what happened. Prior to three days of detailed EUV presentations, three executives from TI, IBM, and Molecular Imprints offered perspectives that do not include a place for this NGL technology any time in the near future.

Hans Stork, SVP and CTO of TI, kicked off the conference with a ruthless analysis of the limits of dimensional scaling:

* Voltage barrier around 1V, regardless of the attempted fixes;
* Speed limitations with logic density scaling (at 65nm nodes, 50% of the delay is in the interconnect, and caused by sidewall scattering and grain boundary effects such that Cu wire resistivity increases nonlinearly) which also induces more variability; and
* Variability (within fab, lot, wafer, die, cell, and transistor) may be systematic, stochastic, or time dependent, but it is increasing, and we must now account for nearest neighbor effects.

Many shrink challenges can be traced to the basic issue of sub-wavelength lithography, which is why the industry has long quested for ~13nm wavelength EUV tools for the 32nm and following nodes. However, due to EUV resist and illumination source supply challenges, the technology looks like it has now been pushed out past 32nm. ASML said that the first prototype Sn-based source will ship next week to one of its two alpha-demo sites, and several papers at SPIE this year discuss source technology.

Even if EUV were ready today, there is no consensus that it would be affordable for mainstream CMOS manufacturing. Answering a question from the audience, Stork invoked the oft-used Concorde jet transport analogy, noting that “We don’t have supersonic air transportation not because we can’t do it -- we don’t have it because it was only cost-effective for a few.” In the case of EUV, those few would be Intel and Samsung, he pointed out. Still, ASML shows cost modeling data that this would be the most cost-effective technology for <32nm node processing.

With delays in EUV, 193 immersion lithography will have to be extended with additional specifications. The “design margin” allowed by lithography, while low at 65nm, seems to effectively disappear by 32nm for a single exposure. Randomly oriented logic layouts—including such features as active jogs, metal and poly local interconnects run in any direction, and variable poly pitch—are the greatest challenge for patterning. “Only when the physical proximity is identical can we expect the performance and functionality to be identical,” said Stork, “and this has a penalty.”

That penalty is “structured layout” concepts, which will almost certainly be needed at 32nm nodes and beyond—e.g., all lines in a given level may be constrained to be parallel. Regardless of the design abstraction level at which the structuring occurs, the most optimistic models show that a highly structured 32nm layout may be only marginally smaller than a nonstructured 45nm design. Double exposure (two masks exposing one resist layer) and double patterning (two masks exposing two resist layers, often using a sacrificial hard-mask) may also be used with structured layouts to increase K₁ in the sub-wavelength litho world.

Stork maintained that design rules are already out of control, and while models to replace rules seem attractive, calibration remains problematic. For example, building an OPC model requires factors to account for the mask, photo process, illumination source, and etch. Any change to any one of these factors requires a new model.

IBM’s director of lithography technology development, George Gomba, gave a keynote presentation on the current status of 193 immersion lithography. Single-exposure i193 will be fine for the 45nm node, and double-exposure/double-patterning extends it at least another two nodes, so as to push out the need for EUV, he said. Curiously, however, it seemed that Gomba had an inability to speak without spin—essentially the takeaway message I got was, "Through the enablement of ...strategic best in class...partners ...commensurate with long-range productivity ... methodologies ...provide a simultaneous high-productivity solution to the marketplace ...posturing this for production in 2007."

The final keynote of the morning by Mark Melliar-Smith, CEO of Molecular Imprints and former leader of Bell Labs and SEMATECH, discussed the current status of nano-imprint lithography (NIL). Throughput estimates show that to achieve ~20 wafers/hour with a step-and-flash tool, pattern-specific pico-liter droplets must be jetted onto the chip. With four imprint heads theoretically downhill-with-the-wind on a good day, Smith believes that the company could build an 80 wph tool. Defect levels are currently 100X greater than specs, which is daunting or trivial depending upon one's perspective. The most promising application for CMOS is direct patterning of dielectrics for dual-damascene interconnects in a single step, in which both the line- and via-levels would be formed at once without a critical etch step.

Lithography will only become more challenging over the next few years, as the industry pushes further into sub-wavelengths of 193nm. Immersion mitigates the need for double-exposure, but only for one node. Though great for optoelectronics, NIL remains problematic for CMOS. Despite significant progress, EUV is not ready, and so the industry will be forced to struggle with greater DFM issues. Consequently, SPIE 2007 includes three days on DFM presentations. — E.K.

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