Ed’s Threads 061020
Musings by Ed Korczynski on 20 October 2006

Future of ICs Seen in Belgium
The beautiful tree-covered campus of the Katholieke Universiteit Leuven is the site of IMEC. I visited the Flemish research institution for its annual progress review meeting and to hear about the first major reorganization in its 20 year history. Partly driven by its growth to approximately 1500 permanent staff and visiting researchers, the re-org primarily aims to break down the conceptual walls between manufacturing technology development, multi-chip packaging, and circuit design. The three formerly independent divisions will be led by Luc Van den hove after being promoted to COO of the new org starting in January.

There are many technical challenges in all three areas, and IMEC thinks that greater overall efficiency will come from keeping all three focused on specific targets. Through materials engineering of transistor gates, contacts, and isolation, we already provide different Vt and leakage levels. A designer can already chose from many embedded memory types. Targeted options for specific applications will increase the number of options, and the shear number of possible combinations will grow exponentially. As an example of a targeted application, finFETs could have advantages over planar transistors for applications in analog, RF, and even embedded-SRAM.

Smaller was almost always better during the era of “simple scaling”: faster, cheaper, and indeed smaller. In the nanometer era, however, area, power/speed, and leakage are now tradeoffs. For example, a recent nano-scale IC designed by IMEC had a target speed of 500MHz at 100mW power consumption, and 95% of the first silicon chips did function. However, due to unpredictable variability in real-world transistors, only 58% of the yielding chips could function at 500MHz or faster, and just 24% consumed less than 100mW at desired speeds, for a final functional and parametric yield of only ~14%.

Some manner of new EDA capability will be needed, just as logic synthesis was added to EDA tools to handle a previous jump in design complexity. Hugo De Man, IMEC Senior Fellow, noted that, “Today we have statistical timing analysis, but not statistical timing synthesis. There is work in this direction, but no movement yet to integrate this into a standard design flow, and it will probably take seven years. It is possible to come up with a methodology that allows you to keep working as we have in the past, but we must have another level of abstraction, and that has not happened yet.”

Until new EDA tools are developed, cross-functional teams like those being established at IMEC will be needed. Designers don’t necessarily need to go back to school to study materials science, and Fab-folks don’t have to become capable of performing advanced logic synthesis, but it truly helps to at least understand the terminology and the basic work-flows of each side. For at least the next seven years, such conceptual bridging will be essential for the creation of nano-scale ICs.

IMEC wants to call all of this “Technology Aware Design” (TAD), since basic awareness of interactions between manufacturing technologies will be essential for the design of nano-scale ICs. As a word-smith, I approve of their accurate term for a complex issue, but since it is at odds with the flood of “DFM” marketing hype generated in the last few years, the term is unfortunately doomed from the start. No matter what term you chose, the work only gets more complicated and organizations like IMEC will be vital to the future of the IC industry. Much of the IC’s future is now routed through Leuven, Belgium.

– E.K.
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061020: Future of ICs Seen in Belgium

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Ed’s Threads 061006
Musings by Ed Korczynski on 06 October 2006

Samsung may sneak IBM back into Apple
Once upon a time, Intel made microprocessor (MPU) chips for PCs running Microsoft operating systems, and IBM made MPUs for Apple Macs. Last year, Apple loudly announced it was switching to Intel for Mac MPUs, and IBM lost a lot of business from one of its major customers. Intel won, and IBM lost, end of story. Right?

Maybe not. We’re now living in a world of “system on chip” (SoC) designs, where the functionalities of multiple discrete IC chips are integrated during the design into a single piece of silicon. The reasons are twofold: we can, and we must. We can create SoCs now that we can design a billion transistors into a single-chip. We must create SOCs for high-unit-volume chips, because the performance improves while the cost is reduced -- keeping all of the circuitry on a single piece of silicon has always been the least expensive way to go if you can make all of the pieces properly function. New electronic functionalities are typically first created as separate chips, but within a few years those functions are usually integrated into a previously existing chip.

We’re also living in a world of “rebranding” and outsourced manufacturing of chips. For example, the custom MPU inside the Microsoft Xbox was designed by IBM and manufactured by Common Platform Alliance (CPA) member Chartered, for a Microsoft-branded chip.

Apple has created a blockbuster iPod product line, currently selling more units and generating more profit than its flagship Mac computers. The company has been issuing new iPod variations every 6-9 months, and they are very profitable, with reportedly >50% gross margin. By comparison, the Xbox is rumored to sell with a negative 30% gross margin -- i.e., Microsoft is losing >$150 on each sale.

To keep the iPod bill-of-materials (BOM) for construction as low as possible, Apple has pushed integration into SoCs. The latest iPod Nano includes a SoC from Samsung that reportedly uses an ARM-core for the MPU. Prior generations of iPods had chips with brand names from Samsung, Wolfson, and Philips (now NXP) on the PCB, but no longer. The latest iPod Nano’s include three chips labeled as “Apple” ICs which are reportedly from these three companies.

Last year, Samsung announced that it had licensed the PowerPC-core IP from IBM for inclusion in SoC designs. Recently IBM announced new low-power PowerPC-cores as well as hardened ASICs for SoCs. IBM’s new 464FP H90 ASIC core is specifically promoted to “allow customers to more easily customize a chip design and have it manufactured with IBM or at Common Platform manufacturing facilities,” i.e., Chartered and Samsung.

AMD, though not in the CPA with Chartered and Samsung, is another partner of IBM’s working on silicon-on-insulator (SOI) instead of bulk silicon wafer manufacturing. President Hector Ruiz is reported to have declared that Apple will buy chips from AMD. It could happen.

Meanwhile, Apple has taken the unusual (for Apple) step of pre-announcing a major new product: iTV. This smallish box is intended to be the center of your new digital living room for 2007. Which MPU will power the iTV? It could easily be a PowerPC-core produced by the CPA, but it might only show “Apple” on the outside package. The same could be said of any future “iMumble” hardware product fielded in the next few years -- Samsung could sneak IBM MPUs back into Apple products.

– E.K.
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061006: Samsung may sneak IBM back into Apple

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Ed’s Threads 060929
Musings by Ed Korczynski on 29 September 2006

Common Platform constellation rolls through town
The “Common Platform Alliance” (CPA) of IBM, Chartered, Samsung, and Infineon gathered to gather customers at the Chartered Technology Forum, Sept. 28, at the Santa Clara Convention Center. The CPA is a complex constellation of companies orbiting IBM in East Fishkill, NY (the single ugliest city name in North America). The CPA would like you to know that 45nm chip production is not for the meek or faint-of-heart, but it you have a 45nm design and don’t already know where you’ll get it fabbed, then you should look them up. You’ll also want to talk to quite a few of their design-for-manufacturing (DFM) software partners -- Blaze DFM’s work to automatically tweak gate-widths to optimize overall chip electrical leakage for Qualcomm was featured in this SST article.

It’s Chartered’s show, but the membership in the CPA is a “4 Musketeers” sort of thing: it’s all for one and one for all, all the time. Thus, IBM and Samsung show up too, and everyone openly discusses collaboration and even some competition. They collaborate on technology requirements and development, design automation, and manufacturing fundamentals. They compete for the same customers based on who has the closest prior relationships, and the more valuable special IP for the specific chip/product requirements -- a customer may need special analog or other circuitry, or special final packaging, for example. Dr. Hokyu Kang, VP of advanced technology development for Samsung Electronics, explained during a press conference that, “we use a ‘background information’ list that each company provides to keep track of how much process and manufacturing IP each company brings to the JDA.”

They seem to walk the talk on all levels. In keeping with the spirit of collaboration, marketing folks from all four companies coordinated meetings and event throughout the day at the Chartered event. Multiple outsourced marketing communications companies also worked behind the scenes to keep things running smoothly.

All of the efforts are devoted to attracting and keeping the shrinking number of big fabless companies, such as Qualcomm, NVidia, and Microsoft. There will certainly be fewer companies designing fewer chips at 65nm and 45nm nodes, and >$1M mask sets and tens of millions of dollars in design costs limit design starts. “Some of the low-volume products that are around today will not exist in these newer nodes. Either their functionality will be directly integrated into another chip, or programmability will allow comparable functionality within a single chip,” explained Franz Neppl, Infineon’s SVP of base technologies and services. “That is one way to address time-to-market and design-cost issues.”

With high levels of FUD (Fear, Uncertainly, and Doubt) associated with IC production at these nodes, the CPA positions itself as the least risky way to get a concept into working silicon. Not sure how to port old IP blocks to the newest nodes? Resources are available. Need help with system integration options? That can be provided. Interested in advanced packages for your chips? Amkor has joined the CPA, too. Not sure what your design-fab tradeoffs may be? Experts will talk to you for a price. You may need to look at circuit layout constraints -- such as orientation with respect to the silicon crystal, or forbidden pitches -- to gain yield in manufacturing. The FUD is based on reality, and any fabless company must make a huge financial bet in starting a new 65nm chip design. Step right up and place your bets; with enough players the house always wins.

– E.K.
posted by [email protected]
060929: Common Platform constellation rolls through town

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