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070323: Integration extends 193nm litho
Ed’s Threads 070323
Musings by Ed Korczynski on March 23, 2007

Integration extends 193nm litho
As thoroughly reported by WaferNews, SST, and Microlithography World, the 2007 SPIE lithography meeting detailed that 193nm wavelength lithographic reduction steppers may be the last mainstream lithographic technology for the semiconductor manufacturing industry. Whether dry or with the wafer under immersion (193i) of a fluid to push the resolution, there really is no other choice besides direct-write. Consequently, process development engineers now look for ways to create ever smaller device features using 193nm litho with clever combinations of other known unit-process steps: thin-film depositions, etches, and plasma surface treatments.

Double-exposure (in which a single resist stack is exposed twice) and double-patterning (with at least one thin-film hard mask, and usually two exposures) with 193nm are now in use and under development in different CMOS fabs. Double- and triple-patterning has been used in the MEMS industry for over 20 years, to allow for all lithography to be completed before complex multi-step etching of physical structures such as membranes and cantilevers.

A classic and well-known integration trick to extend litho is “resist-trim.” Used for gate formation, resist lines defined by lithography are plasma etched to thin them and so achieve linewidths below the resolution of the optics. Various resist-swelling techniques can narrow contact holes below lithographic resolution limits. Applied Materials now claims an anisotropic plasma etch of a hardmask can narrow holes.

Applied Materials now also touts two different hardmask materials: a dielectric advanced patterning film (APF) for most applications, and a 25-30nm thick PVD titanium nitride (TiN) film for integration with low-k dielectrics having porosity of up to 30%. The $2-$3/wafer APF has the amazing ability to “heal” line-edge roughness (LER) from an upper resist layer. Because it is not built out of large molecules like resist, the byproducts of etching the APF are small ligands with sp3 hybrid bonds that coat exposed sidewalls with diamond-like carbon, which preferentially fills in 1-2nm features. Consequently, LER of 2.5 nm in resist becomes just 1.5 nm when etched into the APF.

Applied Materials has developed a complex, self-aligned double-patterning scheme that uses a quadruple-hardmask and a self-aligned spacer nitride with a single litho step:
- Depositing a blanket stack of APF + oxide + APF + nitride on top of poly,
- Coat resist and dry 193nm litho of pattern into resist,
- Trim resist, then etch pattern into nitride and top APF,
- Deposit self-aligned sidewall spacer nitride,
- Etch APF, and then
- Etch poly gate features using remaining spacer nitride.

Improved metrology will certainly be essential to manage any of this new integration. Metrology now controls the process—it doesn’t merely monitor—and it must also provide the vital data to build design and litho models. For example, building an OPC model requires accurate metrology to capture the interdependencies between the mask, resist, and at least one etch. Thus, SPIE now includes thorough sessions on DFM and metrology.

The history of semiconductor manufacturing technology is the history of risk-avoidance at the bleeding-edge of human knowledge. “The industry is overall conservative as any manufacturing industry must be,” commented TI’s Hans Stork in his keynote address at SPIE this year. “We only move to a new material or a new approach if there is no alternative.”

Technologies must hit the sweet spot in the middle of capability/risk/cost, and it’s the overall integrated process that counts. If multiple low-risk and inexpensive process steps can replace a single risky and overall more expensive step, then the reduced cost and risk of the multi-step flow will always be worth the longer fab cycle-time.

—E.K.

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070302: Hatching new fabless business models
Ed’s Threads 070302
Musings by Ed Korczynski on March 02, 2007

Hatching new fabless business models
The old fabless business model is dead...long live the new fabless business models! Tracking recent evolutionary changes to the business of fabless IC manufacturing was the topic on the table at a Feb. 28 luncheon panel discussion hosted by the Fabless Semiconductor Association (FSA) and moderated by Charles DiLisio of D-Side Advisors.

The old fabless business model has broken down and needs to be cast aside, so the argument goes, to give way to two new models and a small number of “virtual IDMs.” The largest of today’s fabless companies—such as nVidia, Qualcomm, Altera, and even Microsoft—basically function like IDMs, with huge staffs to manage their dis-aggregated supply chains doing full-custom chips at advanced nanometer-era nodes. They possess the necessary resources to manage all of the high risks in designing nanometer-era chips themselves on an ongoing basis.

For everyone else working on new chip designs, the key issue is this: who manages the risk in manufacturing? In the old days, the design rules from the foundry captured the risk—if you stayed within the rules, the wafers would yield. Today, with a leading full-custom chip design costing at least $10 million, and with consumer applications needing to hit tight market windows with high volumes, chip designers are faced with a choice: either program a customizable logic chip that someone else has already designed, or do a custom design with some new way of managing risk.

Robert Blake, VP of product planning at Altera Corp., understandably supports the platform-based design model, touting the lack of risk in time-to-market for consumer applications. “Being out first with new capabilities is the difference between being reasonably successful and winning,” he commented. “You have to clearly demonstrate some leadership in delivering technology to the marketplace, but you have to balance the risk.”

The full-custom design option for a small company requires a radically new business model, according to DiLisio. He envisions a “Hollywood movie studio model,” where a “producer” with a “script” and a few star “actors” assembles the rest of a team to make a movie for a set period of time. When the movie is finished—i.e., the chip is designed and yielding in silicon—the team dissolves.

How such a business model would be managed (or even funded by VCs) remains to be seen. To simplify operations, companies have outsourced all non-core-competencies, yet this results in a “simplicity paradox,” according to Jack Harding, chairman, president, and CEO of eSilicon Corp. “It gets harder and harder to manage a dis-integrated supply chain. With the supply chain lengthening, 90% of the people are outside of your direct control,” he pointed out.

To help the chip “producer” manage the risk in future custom designs, the FSA recently released its Hard IP Quality Risk Assessment Tool, which works across seven criteria/categories: IP design, integration, verification, process technology, product documentation, reliability, and test. Raminderpal Singh from IBM's systems and technology group is the technical lead for the project.

A fabless start-up company today can go down one of two roads: either pay one programmable logic company to manage the risk, or keep the risk and manage an ad hoc team to work with the FSA’s new framework. Either way, from the fab perspective, these changes should result in more manufacturable designs, and therefore fewer unhappy customers.

— E.K.

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070302: Hatching new fabless business models

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.