Ed’s Threads 070727
Musings by Ed Korczynski on July 27, 2007

Working together to reach nirvana
SEMICON West hasn’t been a “selling show” (i.e., a tradeshow where you actually sell stuff) for well over a decade, so why do people still bother to attend it? There are still endless meetings and seminars and panel discussions that provide vital connections and information to keep the industry going. Manufacturing ICs with minimal dimensions below 45nm creates technical challenges that combine with consumer-market challenges to create extreme rewards for success and extremely expensive penalties for failure. For any IC fab company to succeed in the future, partners will be needed and new ways of working together will have to become new habits, as detailed in two separate panel discussions held on succeeding days by Praxair Electronics and DuPont Electronic Materials.

The first few decades of the semiconductor industry were based on vertical business integration like that championed by Henry Ford at the carmaker's Rouge Plant, where controlling the stream of raw materials and custom-built equipment resulted in massive economies of scale. Vertical organization under a strong top customer leads to a clear hierarchy of power, and corresponding norms of one-way information flow, dual-source strategies for all suppliers, and limited motivation for fixed relationships.

By the 1990s, however, the global semiconductor industry had became vertically dis-integrated, with separate levels for original equipment manufacturers (OEM) and specialized subsystems manufacturers — yet the mindset of vertical integration typically remained.

Today, we’re in an era where the complexity of manufacturing has increased to the point that even the biggest integrated device manufacturers (IDM) like Intel and IBM and TI have to partner to develop technology. With consortia and joint-development projects (JDP) now driving the creation of most new intellectual property (IP) in the industry, and with the increased costs and risks of nanometer-era IC fabrication, we must develop new habits of working together and sharing information.

Carrying the theme that “In sharing knowledge we can achieve true enlightenment,” Praxair’s July 17th event at SEMICON West featured keynotes by SEMATECH’s Raj Jammy and processing expert John Borland, discussing the technical challenges of 32nm node transistor fabrication. In the panel discussion that followed (which I had the pleasure of moderating), I attempted to express some “Zen-like” ideas about working together in a harmonious ecosystem. More details from the Praxair panel can be found in SST On the Scene video interviews available online.

Meanwhile, DuPont’s July 18th seminar entitled "Technology Partnerships and Tools for the Future" featured presentations by executives from IDMs, OEMs, academia, and a consortium (SEMATECH's Raj Jammy again) on how cooperation is needed to meet the increasingly demanding requirements of advanced ICs.

Mansour Moinpour, materials technology and engineering manager for Intel’s global fab materials organization, showed that even the largest company in the industry with potentially the greatest internal resources has used an ever increasing number of partners over the last decade. Large companies today have typically systematized interactions with universities and other research organizations. “I think the challenge is going to be how to make sure that we facilitate the interaction of the small companies with the universities,” explained Farhang Shadman, Regents Professor of Chemical and Environmental Engineering at the U. of Arizona, and director of its Center for Environmentally Benign Semiconductor Manufacturing. “I think this is very important, because they are in greatest need of research facilities.”

Basic human trust is essential to making deals that can quickly bear fruit, combined with prior aggregate experience, and some manner of mutual benefit on a strategic level. Jammy said that templates and standards have allowed SEMATECH to reduce the time needed to get a signed contract from one-half year down to weeks. John Behnke, VP of process development and transfer for Spansion, commented, “There are some pretty good templates that the legal community and the different corporations begin with, which helps the process. I think it has matured in the last maybe two to three years. So that helps.”

Behnke reminds us that trust is still vital to efficient business, and trust that your ideas will not be stolen is perhaps the most vital. “Let's say that the room is dark and the solution to that is to invent the lightbulb,” he explained. Once the hard work of creating a working lightbulb is complete, “the person who said the room was dark thinks that it's all theirs.” This sort of mindset was not uncommon in the past. Fortunately, it seems that most of us now realize that an attitude of “enlightened altruism”—in which we all work for mutual benefit—really does result in the greatest individual benefit too.

–E.K.

Labels: ecosystem, fab, IC, partner, semiconductor

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070727: Working together to reach nirvana

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Ed’s Threads 070720
Musings by Ed Korczynski on July 20, 2007

HK+MG metrology technology
With High-k (HK) dielectrics and metal-gates (MG) now being ramped into CMOS production at Intel and IBM, much of the excitement at the just finished SEMICON West 2007 in San Francisco centered around manufacturing technologies needed for these new materials. ASM and Imago sponsored seminars on these topics, and much of the discussion in panel discussions sponsored by Praxair and DuPont centered on the challenges of working with these new materials. In particular, setting up affordable in-line metrology for these new ultra-thin materials will be tricky.

Recently departed SEMATECH Fellow Alain Diebold, now a Professor at the U. Albany, provided an overview of the need for HK metrology in a breakfast seminar sponsored by Imago. For HfxSi1-xO2, both x=0.25 and 0.75 are stable structures, which may be regarded as Hf substituted in an SiO2 matrix and Si substituted in an HfO2 matrix, respectively. HK layers in production will likely be just 3-5 atomic layers thick. Since improving hole mobility is inherently difficult, one first possible application of finFETs is to integrate PMOS finFETs with planar nFETs at the beginning of the 32nm node. “We need atom-by-atom characterization and metrology for fins in R&D; today, not later,” informed Diebold.

The U. of North Texas—previously renowned for its jazz music scholarships—inherited an old TI fab and received $11M in funding to invest in cutting-edge metrology tools. TEM can resolve sub-angstroms spatially, but chemical resolution is limited to ~1%. Secondary ion mass spectroscopy (SIMS) provides sub-parts-per-million chemical resolution, but lacks special resolution. Local-electrode atomic probe (LEAP) systems sold by Imago Scientific Instruments provide ~2Å spatial resolution and ~E18 chemical resolution, using full-width-half-maximum (WFHM) measurements of a calculated concentration curves to calculate thickness. Approximately 80nm diameter silicon samples are cut from wafers using a dual-beam FIB, and 6-7 samples can be prepared in an hour by a skilled FIB operator. Dopant “snow-plow” effects in diffusion, quantum well structures, and buried interface roughness can all be analyzed to calibrate in-line metrology techniques. LEAP reconstructions of this HK stack as-deposited and post-anneal show 0.5nm of Hf and O diffusion.

Since LEAP provides excellent resolution but is inherently destructive and relatively slow, it is ideal for R&D; but cannot be used for in-line production control. Still, LEAP and other lab techniques are vital for calibration of production control approaches. “The type of information that you get from R&D helps you set up your in-line metrology, and the two work hand-in-glove, as Howard Huff used to say,” reminded Diebold. With HKMG now ramping in production, there’s a crop of new in-line metrology tools available.

ReVera provides XPS tools that can resolve thickness, composition, profile, and chemical bonding states information from thin dielectric films, and claims customers are using the tool to measure gate-dielectrics and HK storage for memory chips. XPS can measure all elements heavier than He for any film or material up to 100Å thick in any part of the process flow.

After one year of promoting it for high-volume metrology applications such as HK+MG, Metryx claims sales have doubled for its mass monitoring tool, which has sufficient resolution to detect differences in the atomic masses between silicon (28 g/mole) and hafnium (178 g/mole) in hafnium-silicate ALD layers. The company claims wins with customers for process control applications in volume fabs, typically measuring the masses of >60 wafers/hr.

Metrosol’s vacuum ultra-violet (VUV) spectroscopic reflectometer was designed specifically to handle in-line metrology of ultra-thin dielectrics. Two manually-loaded chambers have been in use for over two years at customers, one for hafnium-silicon-oxide films and one for nano-imprint lithography (NIL). The first five beta units of the fully-automated tool will be ready this September. The purchase cost is claimed to be 1/2 to 2/3 of an x-ray or extended range ellipsometer, and typical throughputs are 2x-10x of such systems. (Click for WaferNEWS' interview with CEO Kevin Fahey.)

Since thin-film metrology is pointless if you can’t deposit the material in the first place, the readiness of the industry to begin volume production of chips using HK gate-stacks has been shown by ASM officially releasing its Pulsar ALD chamber for the company’s Polygon cluster-tool. ASM likes to term its ALD variant atomic-layer CVD (ALCVD), though the process and hardware seem quite similar to other single-wafer ALD technologies.

Gate-first HK stacks use a capping layer such as lanthanum-oxide to form a dielectric dipole in the vertical dimension. This cap oxide is hygroscopic, so the stack should be formed without breaking vacuum to eliminate exposure to water vapor. This is just one of the critical integration issues which must be controlled in the formation of HK+MG CMOS transistors. With atomically thin films and complex interdependencies in integration, the “make versus buy” decision for 2^nd-tier fabs will almost certainly fall to buying it, because it just cannot be easily made. “Even if you reverse-engineer the chip, you can’t discern the integration scheme,” explained Glen Wilk, product manager for transistor products at ASM.

Don’t worry if all of this sounds almost too difficult to manage. Professional materials scientists have been working on the research for decades, and we’re now in the era of engineering specific solutions to known problems. Stay tuned for yearly breakthroughs.

—E.K.

Labels: ALCVD, ALD, high-k, HK+MG, LEAP, manufacturing, metrology, XPS

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070720: HK+MG metrology technology

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Ed’s Threads 070713
Musings by Ed Korczynski on July 13, 2007

High-k, low-k, special-k, super-k
SEMATECH has announced that the R&D; organization has developed a “super High-k” dielectric for ICs. How “super” can it be at 30-40 k (double the 15-20 k of hafnium oxide)? How easy might it be to integrate? We can’t guess since the material and its properties beyond the dielectric constant remain secret. All we know is that some people want us to call it “super-k” or “SHK”, and I’m against this as title inflation.

As the semiconductor manufacturing industry pushes the limits of CMOS architectures to ever smaller physical dimensions—45nm node production now ramping—materials properties must improve to ensure proper IC function. New materials are used throughout the chip, yet some of the basic terms used to describe these new materials were never standardized. In particular, the dielectric constant (k)—the measure of a material’s polarizability by a passing electromagnetic wave—was formerly kept in a tight range by using only silicon oxide (k~4) and silicon nitride (k~7) films. With 4-7 established as the “medium” range of k by default, anything <4>7 counts as “High-k” (HK). Note that industry convention capitalizes “High” while not capitalizing “low” in these terminologies. Also note that "k" is properly itallicized but does not always appears as such.

Now 45nm node chips will employ materials with k values ranging from 2.5 to 20, and even lower and higher k materials are under development. Relatively higher k is desired in transistor gates to ensure minimal current leakage when biasing the gate to open the channel, while relatively lower k is desired in intermetal dielectrics (IMD) to ensure minimal coupling and delay to propagating signal pulses.

As the industry has developed low-k dielectrics for IMD, and High-k dielectrics for gates (as well as for memory storage), terminology has been confusing.

Looking first at low-k, the industry first used fluorinated silicon-oxide glass (FSG) with k~3.5, then silicon oxycarbide (SiOC) and silicon-carbon oxyhydride (SiCOH, often pronounced “psycho”) films with k~3.0 for IMD. Since air or vacuum has k of 1, adding pores or gaps to SiCOH as a fraction of the volume proportionally decreases k for the final film. Porous low-k (PKL) films may also be termed ultra low-k (ULK) or extreme low-k (ELK), regardless of where they fall in the 2.0-2.7 range.

Polyimide, benzo-cyclo-butene (BCB), and parylene are all 2.5-3.0 k range films used in passivation and packaging, though they are not commonly termed ULK or ELK. So, for a given chip, it’s possible that a porous SiCOH film of k=2.6 would be termed ULK, while the k=2.6 BCB film used on the same chip is merely “low-k”.

Terminology moving in the other direction was formerly simpler. Starting with k ~7 for silicon nitride as the top end of the “medium” k range, the industry currently uses aluminum oxide and hafnium oxide as HK films in the 8-10 and 15-20 ranges, respectively. Less publicized in recent years but used in volume production nonetheless, ferroelectric RAM (FRAM) fabs use lead-zirconium-titanate (PZT) and barium-strontium-titanate (BST) materials with k values in the 100-300 range. For years, any dielectric with k>7 was simply termed “High.”

Now that SEMATECH wants to call 30-40 the “super” dielectric constant range, what are we to call k>50? Shall we follow the hard-disk drive (HDD) industry terminology for magneto-resistive heads and call PZT films “giant-high-k” and BST films “colossal-high-k” starting now? What about the poor FRAM marketeers who suffered without having these terms to describe their products for so many years—who could they sue for lost brand-value? Why not retroactively inflate terminology for other materials and call graded-SiON and ONO-stacks “special-k?”

In all seriousness, we should employ moderation in terminology, and just call this new material another high-k (HK). In the name of simplification, that to me would indeed be "super."

—E.K.

Labels: dielectric, high-k, IC, interconnect, low-k, metal gate, terms

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070713: High-k, low-k, special-k, super-k

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Ed’s Threads 070629
Musings by Ed Korczynski on June 29, 2007

KLA-Tencor drives productive-information
Inspecting nanometer-scale ICs during fabrication is not easy. Knowing what it is that you’ve found during inspection is even more difficult. KLA-Tencor, long the industry’s top inspection company, has now released a defect-review scanning electron microscope (DR-SEM) to drive down the time to create defect Paretos in volume production—leading to both faster excursion correction and more learning for greater yield. The company also quietly purchased software company FabSolve LLC, which might have something to do with all this.

Terabytes of raw data are generated every day in a high-volume modern fab, and careful methodologies are needed to extract signals out of noise. With too many signals to possibly manage, additional processing is vital to filter, process, and extract a sub-set of “productive” information to solve real manufacturing problems. Productive information—sometimes termed “actionable” information, when allowed by legal departments—can be roughly defined as enabling decision-making within a volume production environment. Time to productive-information (TTPI) is thus a critical metric for any fab. For example, a defect-map from an inspection tool is mere data, while defects-of-interest (DOI) separated from background haze is information, but it is only the ultimate DOI Pareto chart of counts by category that allows for productive decision-making in a fab.

KLA-Tencor has long dominated the inspection tool business, and the company has recently upgraded both darkfield (Puma91XX) and brightfield (28XX) systems to increase sensitivity for 45nm node and beyond production. Once an inspection tool has created a wafer-map of detected defects, the wafer needs to be reviewed in a SEM so as to be able to zoom in on individual defect sites. The SEM images can then be analyzed to classify them into different columns in a Pareto, as well as into dreaded SEM non-visual (SNV) defects (meaning the SEM can’t find or resolve them; “visual” is here used for electron imaging).

Applied Materials has been very successful with its defect-review SEM (DR-SEM), but 45nm resolution limitations have opened up a need for a new generation of tools. For example, <50nm defects identified by an inspection tool are often classed as SNV by current DR-SEM tools. “For the biggest semiconductor manufacturer today, 40% or more of total defect counts end up in the SNV bin, and that’s going up 15%-20% each node,” said Christophe Fouquet, director of marketing at KLA-Tencor. Applied has not yet announced a resolution upgrade to its DR-SEM, which provides a window for KLA-Tencor to release its eDR-5200 product.

“So it’s all to get you to the best possible Pareto in the least amount of time,” explained Fouquet. Reportedly, leading fabs today can create only 2-3 Paretos/hour at the 45nm node, sometimes constrained by tool throughputs, sometimes by automated defect classification algorithms. Fouquet claims that KLA-Tencor’s integrated tool-set can often double the number of Paretos/hour at the 45nm node.

Another fab bottleneck can be inspection recipe setup time. Using a DR-SEM instead of an optical tool shortens inspection recipe setup time and provides optimal filtering-settings (defining the noise floor). Lacking sufficient resolution in sensitivity-tuning, you typically end up setting thresholds either too low and get noise, or too high and miss defects. With increased resolution in the DR-SEM, a single cycle of inspect/review can be used to confidently set an optimum inspection recipe.

The increased resolution is due to a different lens design, which is not novel in concept but is rigorous in implementation. Adding x-ray fluorescence detection capability to the lens design was reportedly not easy, nor was the development of topographic review by replacing two side detectors with a new 360° capability that retains the information for later viewing from any side angle to give optimal contrast. This new tool also can take in the optical information from a brightfield inspection step, providing wavelength information that helps in working with previous-layer defects.

Automated defect classification (ADC) by the DR-SEM is desired, but only partially realized today. For example, if there are ~15 classifications associated with transistor formation, then SEM-ADC may be able to capture four or five but an operator is still needed to manually catch them all. KLA-Tencor’s DR-SEM software allows for learning from operator manual classifications, such that after typically <10 wafers it can automatically classify 80%-90% of DOI at 45nm. The company claims the DOI:SNV ratio increases by a factor of five compared to current tools. When moving to n+1 node wafers, the previous n node defect types are retained while new ones are added to the library.

ADC may be aided by a geographical information systems (GIS) database structure used as a reference for locating and classifying defects. Such a database was acquired by KLA-Tencor on June 28th by purchasing FabSolve LLC, formerly affiliated with Vietnamese-based image processing algorithm company DolSoft.

KLA-Tencor claims that its DR-SEM beta-tools are already in use by tier-1 customers in Taiwan, Japan, Europe, and the US. The cost of these new tools has not been released, but like most of what passes for the new goodness (SM) [buzzphrase servicemark by Ed Korczynski] these days, if you have to ask…you can’t afford it.

—E.K.

Labels: DR-SEM, inspection, KLA-Tencor, productive-information, review, TTPI

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070629: KLA-Tencor drives productive-information

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