Ed’s Threads 071130
Musings by Ed Korczynski on November 23, 2007

PV perspective: Interview with AMAT's solar technology expert

Dr. Charles F. Gay, currently VP and GM of Applied Materials’ solar business group, is a renowned expert in PV technology and business, having been president of Arco Solar, Siemens Solar, and ASE Americas, as well as director of the US Department of Energy’s National Renewable Energy Laboratory (NREL) in Golden, CO. He found time in his busy schedule to talk with me about the incredible growth in solar business, and to explain recent changes in the photovoltaic (PV) technology landscape.

“The speed of innovation has ratcheted up quite rapidly, and there are two themes that have affected the industry over the last several years,” explained Gay. One is the scale of the industry, growing at over 40% over the last decade. This has created a dynamic where a company like Q-Cells can just show up in the market and rapidly rise to be No.2. Suntech at No.3 was virtually nonexistent three years ago.

Secondly, as the business has grown, so has the scale of manufacturing. Until recently, crystalline PV lines mainly ran old 150mm wafer equipment obsoleted from IC lines by newer 200mm tools. Less than a decade ago, a world class PV line was capable of producing fewer than 5MW/yr of cells, while today Sharp alone has over 700 MW/year of total fab capacity. Typical PV lines today are 50-100 MW, and a company wanting additional capacity builds multiple lines on site, or starts locating lines around the world depending upon customer demand.

A 100 MW/year line needs to process such a large area of material that equipment from industries other than IC manufacturing, like FPD or architectural glass, have come into mainstream use. “The process control was there, the history of making machines was there, and the expertise enabled thin-films to come onstream just when the lack of silicon had been threatening a delay in continued growth,” Gay said. Control of uniformity over large areas allows for potential cost-reduction in thin-film PV lines.

Thin-film PV panels have been able to capture an increasingly larger piece of the market. While still only ~10% of the total, it is expected to grow at a faster pace due to sheer economies of scale using large glass panels. Secondarily, thin-film lines may take extra market share while crystalline silicon line production is limited by the near-term global poly-silicon shortage.

Some crystalline solar manufacturers have responded with innovative materials engineering and supply-chain management. Using gettering, diffusion, and blanket etching of a top sacrificial layer, a PV line can essentially pull most of the impurities into a top skin that is removed. This adds fab cost, but allows for the use of less expensive "six-nines" [99.9999%] pure starting silicon that is not in short supply. “People thought maybe we can make silicon from dirty quartz using direct reduction, and maybe the silicon only needs to be six-nines pure, instead of nine-nines,” Gay said. He added that cell efficiency for single crystal is ~22% for the very best quality starting material and fab process, ~18% is a general capability for single crystal silicon, and ~16% for high-purity multicrystalline silicon.

Another example of clever materials engineering in PV is tuning the sheet resistance of the silicon using phosphorous (P) diffusion that is pattern dependent. The spacing of topside aluminum lines is determined by the sheet-resistance of the silicon after P diffusion, but P dopants interfere with the short-wavelength absorption of light. An optimization can be found by tuning the P to be higher under the lines (for reduced contact resistance) and lower between the lines (increasing conversion efficiency).

“Innovation has been happening at a faster pace due to the increased scale,” said Gay. “The size of the market is enabling additional R&D in academia, industry, and government, and also allowing for leaps in manufacturing efficiencies.”

An example of manufacturing efficiency increasing with scale is the production of “water-white” glass panels for thin-film PV. Water-white glass has low concentration of Fe₂O₃ which increases optical transmittance, and results in ~2% more light transmission, explained Gay. However, the global demand for this specialized glass was relatively small, so it was only made in relatively expensive batch furnaces. A few years ago, based on solid demand forecasts for thin-film PV panels, architectural glass companies such as Pilkington, PPG, Cardinal Glass, Asahi, etc. started retrofitting continuous float-lines for water-white production. Glass companies can sell “water-white” glass for a premium over standard green soda-lime, while still offering a cost reduction that could be cents per square foot compared to batch processing.

“All the way across the value chain, from basic science to the infrastructure for installation, there is tremendous activity in solar,” observed Gay. “It’s multiplied to the stage in Germany today there are almost as many jobs in solar as there are in automotive. Solar and wind represent for the first time in history the opportunity for job creation.”

With the global terawatt challenge remaining ahead of us, there’s lots of work to be done.—E.K.

Labels: business, energy, manufacturing, photovoltaic, solar

posted by [email protected]
071130: PV perspective: Interview with AMAT's solar technology expert

Post a Comment

Ed’s Threads 071123
Musings by Ed Korczynski on November 23, 2007

Printed silicon RF-IDs by Kovio
Humans like to tag and track things. This natural tendency has led from physical tags and labels to bar-codes and today radio-frequency identity (RF-ID) chips. There has been controversy over the possibly use of “active” RF-ID tags being used to secretly track people, but simpler “passive” RF-IDs seem inherently much more difficult to secretly track since they generally require a sensor to be in very close proximity. Plus, disposable items just aren’t great at tracking people, so we can unreservedly applaud printed silicon ICs for passive RF-IDs from privately held Kovio, Inc.

Kovio, founded by a team of scientists in the MIT Media Laboratory, has come out of R&D stealth mode with a printable silicon IC technology with first applications for extremely high-volume manufacturing of passive RF-IDs. In an exclusive interview with WaferNEWS, Vikram Pavate, Kovio’s vice president of Business Development, discussed the applications of this new printed IC technology. The only manufacturing details released so far are that minimum linewidths will be around one mil using liquid-phase inorganic “inks” for all film precursors needed to form CMOS silicon thin-film transistors (TFT), and the fact that the substrates will be flexible foils. This combines the low cost of graphics printing with the power of silicon-based semiconductors that can function at frequencies of MHz and above.

Many companies and R&D labs have been aiming at getting the electron mobility—expressed in units of cm2/(V·s)—of organics semiconductors up to the 0.5-1.0 range of amorphous-silicon TFTs. In contrast, Kovio’s all-printed silicon TFTs are claimed to exhibit electron mobility of ~80 cm2/(V·s). The team at Kovio includes technology executives from Spansion along with people from the former Matrix Semiconductor—which pioneered the use of deposited active layers in commercial chips.

“We’ve been able to start with all the conventional materials set used by the semiconductor industry, and creating a new paradigm on how you manufacture circuits. You’re working with dielectrics and metals that people are used to work with,” explained Pavate. “We’re very complementary to traditional silicon; traditional silicon will always address high-end RF-ID and reader chips.”

Based on claimed breakthroughs in nanotechnology and materials science, Kovio has developed functional electronic inks include silicon, doped silicon, metals, and insulators. Combining functional electronic inks with high-resolution graphics printing technologies, Kovio has printed high-performance silicon CMOS TFTs on flexible substrates at a fraction of the cost of conventional lithography-based silicon technology. The significantly lower cost is possible as a result of additive digital printing processes, lower capital expenditures, and faster cycle time.

Kovio’s high mobility CMOS allows for work with synchronous protocols, where the signal-to-noise ratios are better. “With these results we can print CMOS, while most organic electronics have been only PMOS,” said Pravate. “We are the first company to report a printed PMOS/NMOS device.” Kovio's technology is also attractive from an environmental and energy consumption standpoint. “We use 0.05% of the hazardous gases and 25% of the power that a traditional silicon fab would use. Plus, you can print these in a day or two, so there’s a significant cycle-time advantage we get as well,” asserted Pavate.

To accelerate the commercialization of its technology, Kovio has announced two separate joint development and supply agreements with Toppan Forms Co. Ltd., a world leader in printing businesses, printable electronics and digital information technologies, and Cubic Transportation Systems, Inc., a subsidiary of Cubic Corporation, the world's leading turnkey solution provider of automated fare collection systems for public transport.

“Our initial focus is to provide the market with low-cost RF-ID. Then we’ll add sensors and displays working with partners to create what we call item-level intelligence. One example could be a glucose-sensor on a medicine bottle that would inform specific dosing.

The market for passive RF-ID chips for access-cards, library collections, and high-end transit cards is projected to be $2.5B this year. “We are using graphics printing tools, and today most of the industry is using an older generation chip technology to make RF-ID. They use 0.18 or 0.13 micron node processing on fully-depreciated fabs, and their chips still cost 10-15 cents,” asserted Pavate. “How can they meet demand without building new fabs with tool depreciation adding additional cost?”

Pavate says that general consensus is a 5 cent inflection point could really stimulate demand, but even that cost is too high for a lot of mainstream retail or for a shipper like the US Post Office or FedEx. The US Post Office moves ~260 billion units a year, and can only consider RF-ID tags that are very low cost. “For the type of devices we’re talking about, 20-30 micron linewidths is adequate,” explained Pavate, so printed processes should be more than adequate and allow for additional cost-reductions. “You focus on improving the printing speed, or the web-width.”

Retail and pharmaceutical industries turn inventory several times per year, so they require very short delivery times. Kovio will print chips and/or antennas and then ship those to customers who produce final system for end-users. “These are printing fabs, and the first thing you do with printing is you think about co-locating it,” explained Pavate. “I see a path where large apparel or automotive or pharmaceutical manufacturers would have the RF-ID line next to the current factory.” Kovio will start discussing roadmaps in general by 2Q08, with pilot production planned for 2H08. Stay tuned…the world of silicon IC production just got a lot more interesting.

—E.K.

Labels: CMOS, Kovio, passive, printed, RF-ID, RFID, TFT

posted by [email protected]
071123: Printed silicon RF-IDs by Kovio

Post a Comment

Ed’s Threads 071102
Musings by Ed Korczynski on November 02, 2007

Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is devoted to ~€300M annual micro-electronics work. The huge new Minatec fab is also on this site, and any developed technology that appears to be commercially viable will be spun out as a “baby” company; Leti has had over 30 babies so far, of which Soitec has grown up the most. Soitec and Leti still maintain close working relations, with personnel routinely spending one day each week at each others’ sites.

TraciT and PicoGiga were also Leti babies, though both have since been absorbed within Soitec. TraciT works on transferring finished device layers, using a combination of thinning with backgrinders/CMP and the Smart-Cut technique. “The Smart-Cut technique is a toolbox, not a single process,” explained Camille Darnaud-Dufour, VP of Communications for Soitec, who accompanied me on the Leti tour. Smart-cut—using hydrogen implant/anneal—works very well cutting layers up to 1μm thick, but to do 5-10μm you need some temporary bonding and wafer thinning. For the latter applications, Leti works with de-bondable SOI using handle-wafers and temporary adhesives.

Laurent Clavelier, who leads much of the work on new layer-transfer technologies such as wafer-to-wafer GeOI and InP chip-to-wafer heterogeneous integration, graciously took me on a full tour through the 200mm and 300mm fabs, which do both pure R&D and pilot production, with typically ~100 lots of wafers-in-process at any given time, running three shifts 24hrs/day during the week and half of the weekend. The fab is stuffed with standard production tools, such as Applied Materials’ implanters and CVD, ASM for epitaxial growth, Lam etchers, Semitool for ECD, Ebara for CMP, and KLA-Tencor and Veeco metrology tools.

In addition to standard CMOS fab tools, Leti has several unique tools such as a fully configured 200/300mm EVG bonder providing precise control of wafer-to-wafer alignment for work on patterned and device layer transfers. This system provides integrated single-wafer wet cleaning including a megasonic arm, and with control of bonding parameters it can perform automated designs-of-experiments. In addition to standard lithographic steppers, Leti uses e-beam direct-write with a single-beam for precise gate-length formation.

GeOI work now involves transferring not just blanket substrates, but full pMOS Ge FETs, which Clavelier claimed “is the best way to do fully depleted high-performance germanium on insulator.” Leti is also working on a “sequential front-end” process that would form nMOSFETs using strained SiGe as a first layer, and after planarization then compression bond a blanket 0.5μm thin <110> Ge layer on top. The pMOSFETs can then be formed in the transferred Ge layer since they require a maximum processing temperature of just 600°C.

GaNOI work is done in coordination with the PicoGiga people, using a combination of epitaxy and layer-transfer to aim for the highest-brightness blue LEDs. Work on optical interconnects continues for clock distribution on chip. Using indium phosphide (InP) III-V wafers to create laser diodes and detectors, thinned dice are bonded to wafers containing thin film optical waveguide structures.

Leti also pursues work on double-gate MOSFET to make high-power and low Vt devices such as 4T SRAMs. Doing so in planar structures requires the use of buried gates below transferred channel layers, so patterned layer transfer capability is enabling.

For 3D stacking applications, Leti and Minatec work with ST and the U. of Bologna on high-speed chip-to-chip communications through capacitive coupling across a silica bonding layer. Two CMOS wafers, each with nine layers of copper interconnects, can be bonded together face-to-face; one wafer is thinned, and then shallow bind-vias are formed to allow for wire-bonding down to exposed bond pads.

A very novel application of a blanket layer transfer that results in a pattern is controlled by a precise angular misalignment. A few degrees precise twist of a top wafer relative to a bottom wafer results in a crystalline mismatch that forms periodic dislocation strips. Using crystals with cubic orientations exposed on their faces can thus result in orthogonal arrays of dislocation strips with 50nm spacing, and these dislocations can be selectively etched to form orthogonal trench arrays for memory cells.

With so much exciting and ground-breaking work going on, it is a bit surprising that Leti is not more widely known for leading the industry -- though parent organization CEA is comparable to the US’ Sandia National Labs, and the culture of an organization devoted to creating weapons-of-mass-destruction is necessarily rather secretive. Even though Leti mostly pursues commercial technology development today, the legacy of secrecy continues as the default culture and the organization just doesn’t have the habit of self-promotion. Somewhat quietly then, Leti continues to lead.

–E.K.

Labels: compound semiconductor, GeOI, InP, Leti, Minatec, research, SmartCut, SOI

posted by [email protected]
071102: Leti continues to lead research

Post a Comment