Ed’s Threads 071102
Musings by Ed Korczynski on November 02, 2007

Leti continues to lead research
Leti (Laboratoire d’electronique et de technologie de l’information) is conceptually 1/3 of CEA (Commissariat a l’Energie Atomique), with nuclear energy and nuclear bombs the other major sections. The atomic reactors at the Grenoble site have been shut-down and now the entire sprawling campus is devoted to ~€300M annual micro-electronics work. The huge new Minatec fab is also on this site, and any developed technology that appears to be commercially viable will be spun out as a “baby” company; Leti has had over 30 babies so far, of which Soitec has grown up the most. Soitec and Leti still maintain close working relations, with personnel routinely spending one day each week at each others’ sites.

TraciT and PicoGiga were also Leti babies, though both have since been absorbed within Soitec. TraciT works on transferring finished device layers, using a combination of thinning with backgrinders/CMP and the Smart-Cut technique. “The Smart-Cut technique is a toolbox, not a single process,” explained Camille Darnaud-Dufour, VP of Communications for Soitec, who accompanied me on the Leti tour. Smart-cut—using hydrogen implant/anneal—works very well cutting layers up to 1μm thick, but to do 5-10μm you need some temporary bonding and wafer thinning. For the latter applications, Leti works with de-bondable SOI using handle-wafers and temporary adhesives.

Laurent Clavelier, who leads much of the work on new layer-transfer technologies such as wafer-to-wafer GeOI and InP chip-to-wafer heterogeneous integration, graciously took me on a full tour through the 200mm and 300mm fabs, which do both pure R&D and pilot production, with typically ~100 lots of wafers-in-process at any given time, running three shifts 24hrs/day during the week and half of the weekend. The fab is stuffed with standard production tools, such as Applied Materials’ implanters and CVD, ASM for epitaxial growth, Lam etchers, Semitool for ECD, Ebara for CMP, and KLA-Tencor and Veeco metrology tools.

In addition to standard CMOS fab tools, Leti has several unique tools such as a fully configured 200/300mm EVG bonder providing precise control of wafer-to-wafer alignment for work on patterned and device layer transfers. This system provides integrated single-wafer wet cleaning including a megasonic arm, and with control of bonding parameters it can perform automated designs-of-experiments. In addition to standard lithographic steppers, Leti uses e-beam direct-write with a single-beam for precise gate-length formation.

GeOI work now involves transferring not just blanket substrates, but full pMOS Ge FETs, which Clavelier claimed “is the best way to do fully depleted high-performance germanium on insulator.” Leti is also working on a “sequential front-end” process that would form nMOSFETs using strained SiGe as a first layer, and after planarization then compression bond a blanket 0.5μm thin <110> Ge layer on top. The pMOSFETs can then be formed in the transferred Ge layer since they require a maximum processing temperature of just 600°C.

GaNOI work is done in coordination with the PicoGiga people, using a combination of epitaxy and layer-transfer to aim for the highest-brightness blue LEDs. Work on optical interconnects continues for clock distribution on chip. Using indium phosphide (InP) III-V wafers to create laser diodes and detectors, thinned dice are bonded to wafers containing thin film optical waveguide structures.

Leti also pursues work on double-gate MOSFET to make high-power and low Vt devices such as 4T SRAMs. Doing so in planar structures requires the use of buried gates below transferred channel layers, so patterned layer transfer capability is enabling.

For 3D stacking applications, Leti and Minatec work with ST and the U. of Bologna on high-speed chip-to-chip communications through capacitive coupling across a silica bonding layer. Two CMOS wafers, each with nine layers of copper interconnects, can be bonded together face-to-face; one wafer is thinned, and then shallow bind-vias are formed to allow for wire-bonding down to exposed bond pads.

A very novel application of a blanket layer transfer that results in a pattern is controlled by a precise angular misalignment. A few degrees precise twist of a top wafer relative to a bottom wafer results in a crystalline mismatch that forms periodic dislocation strips. Using crystals with cubic orientations exposed on their faces can thus result in orthogonal arrays of dislocation strips with 50nm spacing, and these dislocations can be selectively etched to form orthogonal trench arrays for memory cells.

With so much exciting and ground-breaking work going on, it is a bit surprising that Leti is not more widely known for leading the industry -- though parent organization CEA is comparable to the US’ Sandia National Labs, and the culture of an organization devoted to creating weapons-of-mass-destruction is necessarily rather secretive. Even though Leti mostly pursues commercial technology development today, the legacy of secrecy continues as the default culture and the organization just doesn’t have the habit of self-promotion. Somewhat quietly then, Leti continues to lead.

–E.K.

Labels: compound semiconductor, GeOI, InP, Leti, Minatec, research, SmartCut, SOI

posted by [email protected]
071102: Leti continues to lead research

Post a Comment