Ed’s Threads 080407
Musings by Ed Korczynski on April 7, 2008CNT and graphene dreams may be realCarbon nano-tubes (CNT) are the only viable (pun-intended) new materials being developed to replace copper as the electrical interconnects for future ICs. There are no known room-temperature superconductors, and optical interconnects require relatively slow and expensive lasers and detectors, and CNTs are the future.
The theory and practice of growing CNTs was thoroughly reviewed at this spring’s Materials Research Society (MRS) meeting, and the applications as electronic IC interconnects will be seen at the International Interconnect Technology Conference (IITC) to be held in Burlingame, California in June.
The deadline for submitting late news to IITC is this Friday.
Carbon can form an amazing variety of stable crystals and molecules based on different bond energies and angles between atoms. In crystalline form,
sp2 electron orbitals can form 2D planes of graphite or sp3 electron orbitals can form 3D tetrahedral of diamond. The 2D form of solid carbon shows very interesting properties when reduced down to less than a few atomic layers.
Graphene is one or two atomic layers only, which results in geometrically induced electron energy-band modification and the ability to form semiconducting devices.
Graphene is a great potential “long-shot” technology first reported in January 2006 Solid State Technology…sure to generate many Ph.D. theses and likely to benefit DARPA programs…but still quite a way away from proven as commercially manufacturable.
As Gordon Moore reminds us in this recent interview, “The actual idea of an MOS transistor was patented in the mid-'20s,” though it was not until over 40 years later that Intel started making a business out of it.
Take 60 carbon atoms and you can coax them together into a cage-like spheroid called a “buckyball” or fullerene (C60)—initially predicted by
R. Buckminster Fuller based on the potential for stable bond-angles in regular polyhedra—which has the same 2D form as graphene.
Larger and more complex carbon cage molecules can be formed, and seem to be formed naturally by stars in space. Take a continuous supply of carbon atoms and you can coax them together using a catalyst particle into growing as a nano-tube with that same basic 2D form. You can grow both single-walled CNT (SWCNT) and multi-walled CNT (MWCNT). Both grow off of metal catalyst particles, which must somehow first be deposited in the bottom of vias to form interconnects between lines; making the connection on the top side seems like it will be inherently a bit tricky.
At IITC this year, researchers from MIRAI-Selete and Waseda University (Japan) will show actual integration results for CNT in 160nm diameter vias at temperatures as low as 365°C. The team will report that the CNT fabrication process didn’t degrade a fragile low-
k (2.6) dielectric and that the vias sustained a current density as high as 5.0 MA/cm2 at 105°C for 100 hours with no deterioration.
SEM cross-sections of 160nm-diameter CNT vias fabricated with growth temperatures of (a) 450°C and (b) 400°C (IITC2008 Paper #12.4, “Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current,” A. Kawabata et al.)
One of the reasons that MRS meetings are exciting for materials scientists and engineers is that truly leading results are shown. Oleg Kuznetsov et al.—from Honda Research Institute in Columbus OH (USA) and Goteborg University (Sweden) and Duke University (USA)—presented information on the size-dependence peculiarities of small catalyst clusters and their effect on SWCNT growth. Though exact mechanisms are not fully understood yet, we know that nano-scale catalysts particles play key roles in growth, and that sizes alter growth properties. The general background assumption is a vapor-liquid-solid (VLS) model for growth: carbon in the vapor phase is absorbed into the catalyst particle as a liquid from which solid SWCNT grows out. An observed ‘paradox’ is that with decrease of catalyst size from 3nm to 1nm the required minimum temperature for SWCNT growth increases. Molecular dynamics simulations revealed that reducing the catalyst particle size reduces its solubility of carbon atoms and thereby requires higher temperature for SWCNT growth.
Since the researchers used Fe as the catalyst for SWCNT growth, their rigorous modeling work included a re-working of the classic Fe-C phase diagram where they showed that SWCNTs grow in a liquidous region above the Eutectic point. The Fe-C phase diagram is arguably the foundation of modern materials engineering, since it shows how to make the varieties of steel which are the physical backbone of construction in our age, and is taught in all undergraduate materials science courses. While I haven’t been looking very hard, but this is the first time I’ve seen something new in a Fe-C phase diagram since I left MIT in 1984.
—E.K.
Labels: CNT, graphene, IITC, interconnect, MRS, through-silicon via
posted by
[email protected]
080407: CNT and graphene dreams may be real
Ed’s Threads 20080331
Musings by Ed Korczynski on March 31, 2008
MRS meeting covers nanostuff and microthingsOver 4000 researchers were in San Francisco last week for the annual Materials Research Society (MRS) spring meeting, to discuss advances in materials for electronics, energy, health, and transportation. Over 40 technical session run in parallel, with >10 sessions of interest to the semiconductor manufacturing industry at any given time. Theory and results for new IC memory cells, extensions of CMOS logic, and future quantum-dots and nano-rods were shown.
Graphene still seems like a possible replacement for silicon in ICs.
In his
Kavli plenary lecture in nanoscience, Prof. A. Paul Alivisatos of UC-Berkeley described recent work by his group and others on transformations in nanocrystals. Chemical transformations can be used to obtain complex nanocrystalline structures though sequential chemical operations. In an example, CdSe reacted with Ag+ to form Ag2Se which could then be combined with Cd2+ to completely reverse back to CdSe, while the volume of the nanoparticle was completely preserved. Such cation exchanges can occur in semiconductor nanorods and hollow spheres with shape preservation, but when shapes do transform their final forms are currently difficult to predict.
Much of the new materials work is targeted toward finding nanoscale structures which can switch between two measurable states to function as memory cells. Two of the newer random-access memory (RAM) cell types under development are phase-change RAM (PRAM) and resistive RAM (ReRAM).
With Numonyx now officially launched to commercialize PRAM along with Flash, there were many papers looking at manufacturing process flows to optimize the deposition and programming of the
antimony-telluride (SbTe) family of “calcogenide” materials which undergo thermally-assisted transitions between crystalline and amorphous phases. Independent of the MRS meeting,
materials supplier ATMI recently announced co-development plans with Ovonyx for calcogenide CVD precursors.
ReRAM using metal-oxides as switching elements comes in two fundamentally different variations: one-time programmable through the growth of nano-metallic-filaments, and reversible through ionic transport between electrodes. ReRAM materials may be used in PRAM-like cells, or also used as
the switching element in cross-bar architecture arrays. HP Labs, US NIST, and Hokkaido University all showed advances in hybrid circuits built using cross-bar arrays.
For extensions of CMOS logic, with a somewhat clear path forward in new materials for high-k and metal gates, a lot of research now centers on doping technologies. G. Lansbergen et al. (B3.7) from TU Delft (The Netherlands) along with Purdue (USA), University of Melbourne (Australia), IMEC (Belgium), and Caltech (USA) showed the ability to work with a single Arsenic dopant atom in a p-MOS finFET; their experiments represent the first evidence of the ability to engineer the quantum state of a single-donor electron by surface gate control. While single-ion doping is way beyond today’s fab specs, more precise control is needed for the placement of often <100 atoms for channels and contacts.
Wilfried Vandervorst of IMEC showed that
Laser Spike Anneal (LSA) which is essentially “diffusion-less” calls for re-integration from prior rapid-thermal annealing (RTA) schemes where lateral diffusion is significant. Due to the very low thermal budgets needed to form ultra-shallow junctions (USJ), LSA is more subject to pocket dopant fluctuations than spike anneals. Random dopant fluctuations must be controlled, along with structural variations on gate cross-sections which appear as undercuts and footing. LSA helps equivalent oxide thickness (EOT) scaling for gate dielectrics by elimination of a 2-3Å thick re-growth layer. However, to ensure reliability in gate stacks, an RTA step can be added after LSA to improve the situation somewhat. Looking forward to embedded SiGe, LSA so far induces junction leakage and defects gliding along certain crystalline planes which unfortunately relaxes desired strain. LSA for embedded SiC, however, avoids SiC relaxation which improves the strain retention in nMOS. Gate profile control is critical for diffusion-less USJ, which may mean gate-last integation schemes will be easier to integrate.
Karuppanan Sheker, of SemEquip, presented on how to use cluster-carbon implants to improve the Si:C layer formation. There is ~2% limit to how much C can be substituted in silicon lattice. At the
VLSI Technology Symposium 2007, IBM showed [C]sub of 1.65% with mono-atomic C implants and pre-amorphizing implants (PAI). Using clustered carbon eliminates the need for the PAI and provides [C]sub >2%. The source is two benzene rings in the form of C14H14, which upon striking a silicon crystal in the 6-10keV implant energy range automatically induces amorphization with depth of 20nm-40nm. The greater the amorphous layer thickness the higher the percentage C which can be substitutionally incorporated.
Newer finFET architectures, which may first be used for SRAM arrays, require unique integration flows. Mark van Dal, NXP-TSMC Research Center, showed that when implants into fins amorphized the silicon material, the re-crystallization in complex fin shapes results in scattering and other sources of variability. The exact reason for the device degradation is not known, but using either BF2 or B+Ge implants (both of which induce amorphization) result in more transistor variability. At fin widths of 1µm there is no difference, but for fins <0.1µm wide the effect is clearly seen. When non-amorphizing B implants are used, no device performance degradation is observed.
— E.K.
Labels: CMOS, finFET, graphene, materials research, nano, PRAM, ReRAM
posted by
[email protected]
080331: MRS meeting covers nanostuff and microthings
