Labels: ALD, chemicals, manufacturing, process, SAFC, specialty

posted by [email protected]
080429: SAFC Hitech opens modular scalable plant

Post a Comment

Ed’s Threads 080317
Musings by Ed Korczynski on March 17, 2008

There is no more noise...
There is only signal. In controlling the manufacturing processes used for advanced nano-scale IC, the aspects of metrology which we used to be able to ignore as “just noise” are now essential signal we must control. Where to draw the line, and how close is close are just some of the challenges in ensuring that data streams become productive information for fabs. Metrology sessions at SPIE this year shone fractional wavelengths of light into the darkness of controlling accuracy, too.

When IC features were greater than the wavelength of light used in photolithography—and likewise much greater than a countable number of physical atoms—there were many aspects of manufacturing which we could simply ignore. With the smallest IC feature, typically defined by the minimum half-pitch spacing between lines, now reaching ~45nm (which is less than one-quarter of the 193nm wavelength used in litho) we now experience “second-order” and “third-order” effects which must be controlled.

Vladimir Ukrainstev of Veeco Instruments co-led a panel discussion at SPIE 2008 on the need for CD-SEMs to be accurately calibrated with 3D-AFMs. Researchers have reportedly seen a mere 1° change in the sidewall angle of a device structure result in a 2nm change in the CD measured by a standard 2D SEM. With the allowable budget for CD variation shrunk down to 3nm-4nm, this sidewall angle dependence must be controlled. The greatest risk is in process drift in an etch chamber, where sidewall angle can change spacially (e.g., from the center to the edge of wafers) or temporally (from wafer to wafer over time), which can induce substantial error in the CD-SEM measurement.

With tight feedback loops in advanced fabs, erroneous CD-SEM data can be mistakenly used to set the wrong etch parameters for following lots, which can degrade yield. “Instead of changing CD etch time by the week, we’re changing by the lot or the wafer as part of APC,” explained Kevin Heidrich, Nanometrics’ senior director of new business development, in an exclusive interview with WaferNEWS. Total CD control is ~4nm for all variability; a normal rule of thumb for precision over tolerance is 0.1, so the total budget for metrology is 0.4nm.

All measurement techniques are subject to some error, and even the best 3D-AFM is still subject to tip-wear and calibration. Veeco has been working with 3^rd-party specialists to optimize AFM tips for different applications, with great results reported for various shapes nano-machined from single-crystal silicon for strength and then coated with some manner of a carbon coating for wear-resistance. NIST showed SPIE attendees this year that even with a slow, expensive, and destructive technique like TEM, there is still 0.33nm (standard deviation, 1σ) of the sidewall angle uncertainty. Everything else adds up to 0.63nm of total uncertainty. Calibration is vital to minimize the propagation of uncertainties.

One of the issues in determining the side-wall angle is what portion of the sidewall to include in the analysis. For features with corner rounding, this could be challenging even with ideal 90 degree sidewalls. Just considering 2nm radii of curvature on the top corners of etched polysilicon lines of 32nm to 45nm widths, and ~10% of the linewidth varies with where a CD-SEM draws the line for the edge.

To help control APC in all manner of deposition and removal processes, Nanometrics recently announced the delivery of the company’s 1000^th integrated metrology sub-system; the milestone system was integrated into an advanced plasma etch system used to control gate CD in advanced logic devices.

At SPIE, IBM (Daniel Fischer et al.) showed OPC requirements for 32nm and the metrology tool calibrations need to support this advanced node. Modeling calibration sites per mask level has increased dramatically: normalized to the 90nm node, 65nm had 10×, and 32nm is 100×. There are now multiple CDs per contour, which results in a reduced number of measurement sites per wafer. For tool calibration, fundamental parameters of magnification, rotation, etc. each must be properly considered in modeling. The researchers showed that scanning a line array in orthogonal directions in a CD-SEM induced up to 2% variation in measurement due to the beam’s oval shape. It’s not noise anymore. “The users must understand the measurement techniques and have them constant or have a consistent offset to be able to use the data,” said Fischer. He added that with real device structures, 144nm was seen by a 2D tool while 160nm was measured by a 3D tool, so some manner of rigorous automated edge-detection is essential.

OCD looks very extendable to finFETs, too. SEMATECH and KLA-Tencor presented a paper on metrology for high-k finFETs at SPIE. Using high-k HfSiO thicknesses of 1.5nm and 3nm over Si₃N₄, and using TiN as the metal gate, a thorough DOE of depositions over fins was done. Then using KLA-Tencor's next-generation spectroscopic ellipsometer (measuring 225nm and up) for OCD, and CD-SEM from AMAT and also HR-TEM, cross-checks between the OCD and standard thin-film measurements showed that the offset was ~1nm. For the metal gate measurements, it was found that the TiN optical properties varied due to what is suspected to be some manner of slight oxide formation. Data from dense arrays showed serious offset from the pad areas, so correlations must be considered. Measuring in the fin area seems to provide sufficient resolution for process control for both the high-k and metal-gate depositions. OCD measurement precision was at the 1% level or better, and in good agreement with reference measurements. OCD looks very promising for finFET gate stack characterization.

n&k Technologies has modified the optical path of their spectroscopic ellipsometer tool to add a pinhole lens which narrows the transmitted beam spot size from 400μm to 50μm. Since real-world ICs and photomasks tend to have designed areas with regular 50μm arrays, this opens up the ability to measure many more real structures. Collecting the reflectance and transmission in both s- and p-polarizations using 50μm spots provides four separate signals to be used in determining all the layer thicknesses on the mask, including quart etch dimensions for phase-shift masks.

In pushing the limits of signals, IBM and Hitachi recently announced a unique, two-year joint semiconductor metrology research agreement for 32-nm and beyond characterization and measurement of transistor variations. Engineers from the two companies and Hitachi's subsidiary, Hitachi High-Technologies, will conduct joint research at IBM's Thomas J. Watson Research Center in Yorktown Heights, NY and at the College of Nanoscale Science and Engineering's Albany NanoTech Complex. Combining individual research strengths and IP will help "reduce the significant costs associated with research needed to advance the next generation of chip technology," said Bernie Meyerson, VP of strategic alliances and CTO for IBM's systems & technology group, in a statement.

Rudolph Technologies has become the first OEM to join SEMATECH's Metrology Program headquartered at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The initial program addresses a range of issues, including the metrology of thin films and metal gate stacks; wafer front, back, and edge macro defect inspection; and inspection and metrology for through silicon vias (TSV) and three-dimensional integrated circuits (3DIC).

-- E.K.

Labels: accuracy, CD, fab, manufacturing, metrology, noise, SEM, semiconductor, SPIE

posted by [email protected]
080317: There is no more noise...

Post a Comment

Ed’s Threads 071130
Musings by Ed Korczynski on November 23, 2007

PV perspective: Interview with AMAT's solar technology expert

Dr. Charles F. Gay, currently VP and GM of Applied Materials’ solar business group, is a renowned expert in PV technology and business, having been president of Arco Solar, Siemens Solar, and ASE Americas, as well as director of the US Department of Energy’s National Renewable Energy Laboratory (NREL) in Golden, CO. He found time in his busy schedule to talk with me about the incredible growth in solar business, and to explain recent changes in the photovoltaic (PV) technology landscape.

“The speed of innovation has ratcheted up quite rapidly, and there are two themes that have affected the industry over the last several years,” explained Gay. One is the scale of the industry, growing at over 40% over the last decade. This has created a dynamic where a company like Q-Cells can just show up in the market and rapidly rise to be No.2. Suntech at No.3 was virtually nonexistent three years ago.

Secondly, as the business has grown, so has the scale of manufacturing. Until recently, crystalline PV lines mainly ran old 150mm wafer equipment obsoleted from IC lines by newer 200mm tools. Less than a decade ago, a world class PV line was capable of producing fewer than 5MW/yr of cells, while today Sharp alone has over 700 MW/year of total fab capacity. Typical PV lines today are 50-100 MW, and a company wanting additional capacity builds multiple lines on site, or starts locating lines around the world depending upon customer demand.

A 100 MW/year line needs to process such a large area of material that equipment from industries other than IC manufacturing, like FPD or architectural glass, have come into mainstream use. “The process control was there, the history of making machines was there, and the expertise enabled thin-films to come onstream just when the lack of silicon had been threatening a delay in continued growth,” Gay said. Control of uniformity over large areas allows for potential cost-reduction in thin-film PV lines.

Thin-film PV panels have been able to capture an increasingly larger piece of the market. While still only ~10% of the total, it is expected to grow at a faster pace due to sheer economies of scale using large glass panels. Secondarily, thin-film lines may take extra market share while crystalline silicon line production is limited by the near-term global poly-silicon shortage.

Some crystalline solar manufacturers have responded with innovative materials engineering and supply-chain management. Using gettering, diffusion, and blanket etching of a top sacrificial layer, a PV line can essentially pull most of the impurities into a top skin that is removed. This adds fab cost, but allows for the use of less expensive "six-nines" [99.9999%] pure starting silicon that is not in short supply. “People thought maybe we can make silicon from dirty quartz using direct reduction, and maybe the silicon only needs to be six-nines pure, instead of nine-nines,” Gay said. He added that cell efficiency for single crystal is ~22% for the very best quality starting material and fab process, ~18% is a general capability for single crystal silicon, and ~16% for high-purity multicrystalline silicon.

Another example of clever materials engineering in PV is tuning the sheet resistance of the silicon using phosphorous (P) diffusion that is pattern dependent. The spacing of topside aluminum lines is determined by the sheet-resistance of the silicon after P diffusion, but P dopants interfere with the short-wavelength absorption of light. An optimization can be found by tuning the P to be higher under the lines (for reduced contact resistance) and lower between the lines (increasing conversion efficiency).

“Innovation has been happening at a faster pace due to the increased scale,” said Gay. “The size of the market is enabling additional R&D in academia, industry, and government, and also allowing for leaps in manufacturing efficiencies.”

An example of manufacturing efficiency increasing with scale is the production of “water-white” glass panels for thin-film PV. Water-white glass has low concentration of Fe₂O₃ which increases optical transmittance, and results in ~2% more light transmission, explained Gay. However, the global demand for this specialized glass was relatively small, so it was only made in relatively expensive batch furnaces. A few years ago, based on solid demand forecasts for thin-film PV panels, architectural glass companies such as Pilkington, PPG, Cardinal Glass, Asahi, etc. started retrofitting continuous float-lines for water-white production. Glass companies can sell “water-white” glass for a premium over standard green soda-lime, while still offering a cost reduction that could be cents per square foot compared to batch processing.

“All the way across the value chain, from basic science to the infrastructure for installation, there is tremendous activity in solar,” observed Gay. “It’s multiplied to the stage in Germany today there are almost as many jobs in solar as there are in automotive. Solar and wind represent for the first time in history the opportunity for job creation.”

With the global terawatt challenge remaining ahead of us, there’s lots of work to be done.—E.K.

Labels: business, energy, manufacturing, photovoltaic, solar

posted by [email protected]
071130: PV perspective: Interview with AMAT's solar technology expert

Post a Comment

Ed’s Threads 070720
Musings by Ed Korczynski on July 20, 2007

HK+MG metrology technology
With High-k (HK) dielectrics and metal-gates (MG) now being ramped into CMOS production at Intel and IBM, much of the excitement at the just finished SEMICON West 2007 in San Francisco centered around manufacturing technologies needed for these new materials. ASM and Imago sponsored seminars on these topics, and much of the discussion in panel discussions sponsored by Praxair and DuPont centered on the challenges of working with these new materials. In particular, setting up affordable in-line metrology for these new ultra-thin materials will be tricky.

Recently departed SEMATECH Fellow Alain Diebold, now a Professor at the U. Albany, provided an overview of the need for HK metrology in a breakfast seminar sponsored by Imago. For HfxSi1-xO2, both x=0.25 and 0.75 are stable structures, which may be regarded as Hf substituted in an SiO2 matrix and Si substituted in an HfO2 matrix, respectively. HK layers in production will likely be just 3-5 atomic layers thick. Since improving hole mobility is inherently difficult, one first possible application of finFETs is to integrate PMOS finFETs with planar nFETs at the beginning of the 32nm node. “We need atom-by-atom characterization and metrology for fins in R&D; today, not later,” informed Diebold.

The U. of North Texas—previously renowned for its jazz music scholarships—inherited an old TI fab and received $11M in funding to invest in cutting-edge metrology tools. TEM can resolve sub-angstroms spatially, but chemical resolution is limited to ~1%. Secondary ion mass spectroscopy (SIMS) provides sub-parts-per-million chemical resolution, but lacks special resolution. Local-electrode atomic probe (LEAP) systems sold by Imago Scientific Instruments provide ~2Å spatial resolution and ~E18 chemical resolution, using full-width-half-maximum (WFHM) measurements of a calculated concentration curves to calculate thickness. Approximately 80nm diameter silicon samples are cut from wafers using a dual-beam FIB, and 6-7 samples can be prepared in an hour by a skilled FIB operator. Dopant “snow-plow” effects in diffusion, quantum well structures, and buried interface roughness can all be analyzed to calibrate in-line metrology techniques. LEAP reconstructions of this HK stack as-deposited and post-anneal show 0.5nm of Hf and O diffusion.

Since LEAP provides excellent resolution but is inherently destructive and relatively slow, it is ideal for R&D; but cannot be used for in-line production control. Still, LEAP and other lab techniques are vital for calibration of production control approaches. “The type of information that you get from R&D helps you set up your in-line metrology, and the two work hand-in-glove, as Howard Huff used to say,” reminded Diebold. With HKMG now ramping in production, there’s a crop of new in-line metrology tools available.

ReVera provides XPS tools that can resolve thickness, composition, profile, and chemical bonding states information from thin dielectric films, and claims customers are using the tool to measure gate-dielectrics and HK storage for memory chips. XPS can measure all elements heavier than He for any film or material up to 100Å thick in any part of the process flow.

After one year of promoting it for high-volume metrology applications such as HK+MG, Metryx claims sales have doubled for its mass monitoring tool, which has sufficient resolution to detect differences in the atomic masses between silicon (28 g/mole) and hafnium (178 g/mole) in hafnium-silicate ALD layers. The company claims wins with customers for process control applications in volume fabs, typically measuring the masses of >60 wafers/hr.

Metrosol’s vacuum ultra-violet (VUV) spectroscopic reflectometer was designed specifically to handle in-line metrology of ultra-thin dielectrics. Two manually-loaded chambers have been in use for over two years at customers, one for hafnium-silicon-oxide films and one for nano-imprint lithography (NIL). The first five beta units of the fully-automated tool will be ready this September. The purchase cost is claimed to be 1/2 to 2/3 of an x-ray or extended range ellipsometer, and typical throughputs are 2x-10x of such systems. (Click for WaferNEWS' interview with CEO Kevin Fahey.)

Since thin-film metrology is pointless if you can’t deposit the material in the first place, the readiness of the industry to begin volume production of chips using HK gate-stacks has been shown by ASM officially releasing its Pulsar ALD chamber for the company’s Polygon cluster-tool. ASM likes to term its ALD variant atomic-layer CVD (ALCVD), though the process and hardware seem quite similar to other single-wafer ALD technologies.

Gate-first HK stacks use a capping layer such as lanthanum-oxide to form a dielectric dipole in the vertical dimension. This cap oxide is hygroscopic, so the stack should be formed without breaking vacuum to eliminate exposure to water vapor. This is just one of the critical integration issues which must be controlled in the formation of HK+MG CMOS transistors. With atomically thin films and complex interdependencies in integration, the “make versus buy” decision for 2^nd-tier fabs will almost certainly fall to buying it, because it just cannot be easily made. “Even if you reverse-engineer the chip, you can’t discern the integration scheme,” explained Glen Wilk, product manager for transistor products at ASM.

Don’t worry if all of this sounds almost too difficult to manage. Professional materials scientists have been working on the research for decades, and we’re now in the era of engineering specific solutions to known problems. Stay tuned for yearly breakthroughs.

—E.K.

Labels: ALCVD, ALD, high-k, HK+MG, LEAP, manufacturing, metrology, XPS

posted by [email protected]
070720: HK+MG metrology technology

Post a Comment

Ed’s Threads 070420
Musings by Ed Korczynski on April 20, 2007

Solar cheerleading for fun and profit
Mike Splinter, president and CEO of Applied Materials (AMAT), is a great solar cheerleader, and he rightly urges us to consider the energy future for our children and grandchildren. In a recent presentation organized by the Commonwealth Club in Silicon Valley, he stumped for US government tax incentives for solar energy investments, and proposed that 25% of new government demand for electricity should be met by renewable sources such as photovoltaic (PV) panels.

Splinter is not merely a visionary altruist in these matters, since thin-film PV represents the next major growth opportunity for his company. As the IC manufacturing industry has matured, AMAT’s previous 20% annual growth has slowed to ~10% and new high-growth markets are needed to increase growth forecasts back to historic “outperform” levels.

AMAT has made significant investments over the last decade to acquire companies with technologies that support general manufacturing: metrology, gas-effluent abatement, and computer-integrated manufacturing (CIM) software and manufacturing execution systems (MES) for managing lots of substrates and shuttling lithographic reticles around. In addition, AMAT built the “Mayden Technology Center” as a showcase for selling special integrated process recipes in addition to the free general recipes included with all new hardware.

Semiconductor manufacturing fabs want to control their own technologies and supply chains, so they’ve paid for processes from other fabs but almost never from an equipment supplier. Solar cell manufacturing lines require relatively less technology but more classic industrial engineering, and buying an integrated and committed process along with a turn-key physical production line makes a lot of sense. In addition to general thin-films manufacturing technology, AMAT has deep experience with handling the largest FPD substrates in the world through its subsidiary Applied-Komatsu Technology (AKT).

“The latest generation of our tools can pattern six 50” TVs on a glass substrate,” almost the size of a garage door, Splinter told the Commonwealth Club audience. “With innovation we can provide an inflection point for solar energy, to make solar competitive with all other sources of electricity generation,” he championed, and suggested that his company’s technologies may lead to 2x-4x cost-reductions in thin-film PV manufacturing.

Solar sources currently provide <0.1% of the 5 TeraWatts of energy used globally each year. A trillion US$ will be spent on new electricity generation capacity worldwide in 2007, and an average 1GW-capacity coal plant emits as much CO2 as 1 million cars. Today in the US, all renewable energy is only 2% of the total. “The planet’s clock is ticking, and I hope that that ticking is the heartbeat of the planet and not something much worse,” said Splinter.

AMAT is working to set up solar panel fabs for customers in China, India, and Spain, which together represent 20% of the world’s new PV manufacturing capacity. In 2006, the solar manufacturing industry added 2GW capacity to bring the world up to 8GW total; by 2010, a $50B forecast annual investment should build total manufacturing capacity to 25GW. If just 5% of the new demand forecast for electricity worldwide would be met by solar, it would require a total $150B investment. All forecasts for future PV demand are “insatiable” for both the near- and long-term. If you're looking to invest a billion dollars somewhere, a turn-key thin-film PV manufacturing line from AMAT seems like it would provide a solid return on investment (ROI).

Specific public policy changes to help solar investment include extending the home income-tax credit, establishing a net metering law at the federal level, and mandating that 25% of electricity consumption by governments should be from renewable sources. “America is behind the rest of the world in solar energy adoption, and that’s just not acceptable. What are we waiting for?” asked Splinter, “I think you’ll agree that we have to stop making excuses.”

— E.K.

Labels: electricity, energy, manufacturing, photovoltaic, PV, solar, thin-film

posted by [email protected]
070420: Solar cheerleading for fun and profit

Post a Comment