Ed’s Threads 080602
Musings by Ed Korczynski on June 2, 2008

IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) were discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes (CNT) along with new copper barrier materials.

3D with TSV may be considered as the ultimate interconnect concept, since stacked chips provide optimal functionality/volume, and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV and the many variations thereof have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, “via-first” TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, “3D is such a ‘silicon-centric’ process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here.”

Fraunhofer IZM (Institute for Reliability and Microintegration) in Munich has been leading the world in 3D-IC work for over ten years, and researchers from there have been developing detailed system-level heterogeneous integration schemes for wireless applications (for the European 3D integrated sensor program “e-CUBES”). Their target is die-to-wafer (D2W) stacking of a tire pressure monitoring system (TPMS). The wafer has the microcontroller chips, onto which are stacked chips for the RF transceiver, pressure sensor, and bulk acoustic resonator (BAR). For TSV, they integrate chips with both solid metal trenches (typically W filled ~20 µm deep) or hollow vias coated with doped poly-silicon (through the 300 µm thick pressure sensor).

Researchers from Georgia Tech built upon work they first showed three years ago at IITC, and together with IBM and Nanonexus showed real results of using integrated microchannel cooling to remove heat from 3D-IC stacks. Fluidic microchannels were fabricated at the wafer-level using four lithography steps, and the resulting chips showed thermal resistance of just 0.24°C/W compared to 0.6°C/W for equivalent 65nm node air-cooled chips. With reduced thermal resistance, significant advances in speed, power, and/or operating temperature can be achieved; for example, power could be reduced ~20% at the same frequency, or the frequency could increase 10% at the same power.

Basic materials integration challenges of 3D integration were shown in two presentations by IMEC. Micro-Raman spectroscopy (µRS) was used to determine the plastic yield criterion for an accurate finite element modeling (FEM) of the stress near Cu-filled TSV. Due to the inherent mismatch between CTE of Cu (16.7 ppm/°C) and Si (2.3 ppm/°C), some strain will be inherent, and it may degrade electrical carrier mobility. Defining an “exclusion zone” of transistors from the TSV such that mobility degrades <5%,>
IMEC researchers also looked at reliability in a presentation on “Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking.” Both Cu-Sn and Co-Sn were shown to withstand 1000 hours of testing at the extremely aggressive conditions of 150°C and 0.63mA/µm2).

Scott Pozder of Freescale Semiconductor showed an excellent poster on Cu-Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding of flipped dice on a wafer. After D2W bonding using Cookson F602 material at micropad pitches of 59, 64, and 69µm, the robustness of the bond was shown by grinding the bonded dice to 50µm thin using a Disco Hi-Tec tool. While no TSV are used in this die-to-wafer stack, this pragmatic approach based on standard unit-processes which can be found in the open foundry market shows one clear way forward toward 3D today.

Tohoku University researchers showed one way to cut costs in D2W bonding: use a rough lithographic step to form hydrophobic and hydrophilic areas on the wafer, add an aqueous coating and then roughly place the dice. The surface tension of the liquid induces the dice to self-align, and control of the ambient can allow for the liquid to evaporate which temporarily bonds the dice to the wafer. The average alignment accuracy on 100 dice was ~0.5µm, with most dice aligned within <1µm and all <1.5µm.

D2W stacking of 3D chips allows for the used of known good dice (KGD) and the associated minimization of yield losses anticipated with wafer-to-wafer (W2W) stacking. D2W stacking technology will first follow Freescale’s lead by flipping the top die for two levels of silicon, but TSV and three or more levels will certain follow.

Much of the limitation in the use of TSV today remains with the designers; lacking EDA tools, it is not only difficult to optimize a design for 3D, it is challenging to just try to quantify the potential benefits in advance. Until EDA tools are ready the greatest potential value of 3D stacking will not be seen, and most commercial TSV will continue to be used for memory stacks and CMOS image sensors.

This is the last year in which interconnect technologists living in the San Francisco bay area have the exclusive luxury of the International Interconnect Technology Conference being local. Next year (June 1-3, 2009), the 12th IITC will occur in Sapporo, Japan at the Royton Sapporo hotel. The 2010 meeting will be back in the San Francisco bay area, and then the 2011 meeting is expected to occur somewhere in Europe.

—E.K.

Labels: 3D, IITC, interconnect, silicon, stack, through-silicon via, TSV

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080602: IITC shows the way to 3D

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Ed’s Threads 080222
Musings by Ed Korczynski on February 22, 2008

TSV forecast for millions of wafers
Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, Through Silicon Via Technology: The Ultimate Market for 3D Interconnect, provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman.

The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.

In so doing, the wire-bonds are not in any way limits on system performance, since flip-chip bumps and re-distribution layers (RDL) are still used to route signals from chip to chip within the package. Intel has announced that its newest 45nm microprocessor chip is the first to use a thick copper RDL layer along with a polymer interconnect dielectric (presumably spun-on). A thinned memory cache chip with metal bumps (presumably C4NP or equivalent) can then be flipped onto the microprocessor and lead-free connections re-flowed to the RDL for low-latency electrical interconnects. Wire bonds then connect the stack to the package pins through an interposer.

An interposer today is commonly built-up using thin-film laminates, but there is renewed interest in the use of silicon as interposers…which would require TSV. Many companies, including MEMS foundries and equipment suppliers, today offer foundry services to create silicon interposers containing TSVs. Silicon is a wonderful material to use as an interposer between silicon chips: same coefficient of thermal expansion eliminates shear stresses on bumps due to heating, excellent relative thermal conductivity to help heat leave the chips, and excellent mechanical strength. The only problem has been the cost compared to build-up laminates. If costs can be reduced, then demand should be very elastic for silicon interposers with TSV, and we could see interposers instead of product wafers as the main near-term market for silicon TSV outside of memory stacks.

Image sensors for camera modules are already in volume production, with major investments by Tessera and Micron in wafer-level-packaging TSV manufacturing technology. The next volume application seems to be memory stacks, but it is only high-cost niche IC applications today that can justify the added cost of TSVs over wire-bonds. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.

Flip-chip was first introduced by IBM in the late 1960s, and it took approximately 40 years for the technology to become dominant such that more silicon wafers end up flipped instead of wirebonded today. TSV technology is already in use, but it will probably be decades before the majority of chips use it as a solution to the cost/performance trade-off challenge. The official semiconductor silicon wafer demand forecast is for ~10 billion sq.in. of silicon by the year 2010, which corresponds to ~200 million silicon wafers (in 200mm wafer equivalents) to be fabbed. It is unlikely that more than a few million of them will need internal TSV, but if costs can be reduced it is possible that many more could use silicon interposers with TSV.

—E.K.

Labels: blind TSV, interconnect, interposer, silicon, through-silicon via

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080222: TSV forecast for millions of wafers

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Ed’s Threads 071217
Musings by Ed Korczynski on December 17, 2007

Post-FET future discussed at IEDM
Silicon-based CMOS FETs will still be used in commercial ICs in twenty years, but it’s likely that completely new devices will also be in production. It seems highly likely that nMOS and pMOS FET “switches” will be used for mainstream logic and memory until 2015-2020, when such things as cross-bar architectures and quantum diodes may be needed. This is the group opinion of the world’s leading IC fab researchers, as discussed in a 2007 IEDM evening panel discussion moderated by Prof. Dimitri Antoniadis of MIT: “Looking Beyond Silicon -- A Pipe Dream or the Inevitable Next Step?”

The industry will reach the practical limits of scaling planar bulk CMOS at different nodes for high-power logic, low-operating power logic, low stand-by power (LSTP) logic, and memory applications. “Transistor pitch scaling will be increasingly difficult due to stronger impact of parasitics and less effective stress engineering. Even if we can do it, power might limit what can be exploited," opined Wilfried Haensch of IBM. Vertical scaling may be required to minimize parasitic capacitance, and high-mobility channel materials must provide the same or better density scaling potential as silicon devices to be attractive. Inherent variability in sub-22nm node devices will be daunting: pattern variation, random discrete dopants, the number of charges per unit device, and interface roughness (poly grain boundaries, high-k morphology, impurity scattering, etc.).

As an example of tough near-term scaling limits, for a physical gate length of 22nm (effective length 16nm), IBM saw that the extrinsic switching time depended upon the current flux through narrow raised source/drain (S/D) regions, with relatively faster switching in short and wide S/D. “There is no new switch in site,” declared Haensch. “All candidates are either non-manufacturable or they can not be wired up.” Lacking a replacement to the silicon FET, system performance will continue to increase with respect to historical trends due to architectural solutions -- i.e., we’ll have systems with many ‘light-weight’ task-specific cores.

Akira Toriumi of the U. of Tokyo gave his educated opinion -- based on first principles of manufacturing he learned at Toshiba -- as to the best directions to go for a post-silicon future. He thinks that silicon microelectronics research will end in 2015, but any new materials, processing, and devices should be simple. “A one-dimension device like a wire, I don’t believe will be a solution; finFET will be a good candidate,” he said. He also advocates the use of germanium instead of compound semiconductors for new channels. “People are talking about Ge for pMOS and III-V for nMOS," he noted, "but why don’t we challenge Ge CMOS? We can get metal S/D Ge nFETs.” For scaling we need to consider not just channel materials but also contact materials for these new channels.

We are now in a world using digital computing solutions that is "very safe and reassuring,” said Jean-Philippe Bourgoin of CEA-LETI. “If we look back at the work of von Neumann and Turing they had to understand the theory much more than we do now.” Audience member Paolo Gargini of Intel interjected that according to the theory of Heisenberg’s Uncertainty principle, Intel’s planned FET scaling will be limited in the year 2020. A member of Gargini’s research group mentioned the crossbar architecture under development in Stan Williams’ Lab at HP as a likely eventual replacement for the FET. (See my Jan. 16, 2007 Ed's Thread for cross-bar architecture and processing details, based on a late 2006 tour of the lab.)

The next afternoon (Session 34, "CMOS Devices -- Advanced Device Structures"), the far limits of CMOS FET technology were shown by Samsung as experimental results of uniaxially strained {110} silicon nanowire transistor (SNWT) channels using an embedded SiGe Source/Drain for greatly improved pMOS performance. Starting with either SOI or bulk silicon wafers, they first grow embedded SiGe (20-40nm thick) and then Si. After hardmask patterning and a clever sequence of etching, the bottom of the grown Si {110} has become SNW floating above the removed SiGe, but the SiGe beneath the S/D remain, and the inherent SiGe/Si lattice-mismatch compressively stresses SNW to provide 1534μA/μm for pMOS. They saw nFET performance only ~15% lower regardless of {110} or {100} orientation, so good overall CMOS results are obtainable using {110}.

Beyond FETs and cross-bar architectures lies a technology concept still mostly disbelieved by the mainstream: quantum electronics. The IEDM plenary session included a talk by Hiroyuki Sakaki, from the Toyota Technological Institute at the U. of Tokyo, on “Roles of Quantum Nanostructures on the Evolution and Future Advances of Electronic and Photonic Devices.” By controlling the electrons within nanoscale layered structures, quantum confinement results in effective two-dimensional electrons and the ability to form devices such as resonant tunneling diodes, quantum wire FETs, quantum dot lasers, and planar superlattice FETs.

However, commercial quantum electronics still remains out in the future. Use of carbon nanotubes (CNT) grown from catalyst particles shows promise, “but it has been very difficult to control the site selection, as well as other parameters,” according to Sakaki. Charge storage phenomena in quantum dots using either Si or InAs appear like the most likely near-term applications. Though if this is merely an extension of flash memory cell technology, does it really count as “quantum electronics?”

In 20 years, will we see a non-FET-based computer? The aggregate opinion seemed to be “yes,” but don’t expect people in the industry who have lived with it forever to be able to think “outside the FET” and develop something revolutionary.

-- E.K.

Labels: device, electronic, FET, germanium, IEDM, more-than-Moore, quantum, silicon

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071217: Post-FET future discussed at IEDM

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Ed’s Threads 070907
Musings by Ed Korczynski on September 7, 2007

Lam & Novellus both strip wafer edges
This is a tale of two companies, two machines, and two different ways to solve one related problem: wafers have edges. Silicon wafer edges perturb plasma flows in process chambers, and so induce inherent non-uniformities in processing. Silicon wafer edges are seemingly the main source of defects for immersion lithography. Advanced fabs today typically specify a 2mm edge exclusion for wafers, and Novellus and Lam have responded with new hardware to dry strip edges.

Novellus’ downstream dry edge strip. Depth-of-focus along with etch-rate selectivity challenges have led to the need for hardmasks in advanced IC lithography. The hardmask material must be properly chosen for selectivity to the underlying layer to be etched. In many cases, it can be an amorphous carbon PECVD thin-film that is “ashable” (a misnomer since it can be dry stripped without any ash-like residue remaining). A wide variety of hydrocarbon precursors may be used, and deposition parameters must be properly controlled to ensure the final film structure is composed of sp2 carbon-bonds for transparency and film stability. “We’re getting 20:1 selectivity, and extinction coefficient value at 633nm of 0.11,” claimed Julian Hsieh, senior director of product management for the dielectrics business group at Novellus Systems.

To eliminate any edge particles that could kill dice, the Vector Express PECVD tool from Novellus now provides a new dry edge-bead removal (EBR) capability into the outgoing loadlock (which SST recently reviewed). Using an off-the-shelf downstream plasma generator to crack O2 into mono-atomic oxygen (Fig.1), amorphous carbon (red in the figure) is stripped off the wafer edge while the top-surface is masked by center shield hardware.

Field-retrofittable to the Vector platform, the EBR has additional potential applications. Since mono-atomic oxygen is extremely reactive, it may be able to clean other PECVD films off of the edge/bevel of wafers. ”If you have this capability you may be able to use it to solve other problems,” admitted Hsieh.

In addition to clean wafer edges, it’s essential that deposited film properties remain constant all the way to the 2mm edge exclusion. Ensuring a uniform deposition environment across the wafer—in terms of temperature, plasma energy parameters, and precursor flows—requires careful optimization of chamber hardware. Consequently, Novellus modified the Vector Express chamber hardware to include new plasma confinement shields.

Lam’s plasma ring edge strip. Also using a physical shield, Lam Research Corp. now sells a plasma edge clean module that can be part of a cluster on the company’s 2300 hardware platform. A capacitively coupled plasma is shielded from the wafer topside by a shield precision engineered to float fractions of a millimeter above the wafer surface (a gap too small to be seen in Fig.2). No electrostatic chuck is used to minimize cost.

“If we as an industry had recognized the value of bevel clean, we would have done it earlier,” said Rick Gottscho, group VP and GM of Lam's etch business, noting that this market opening started with Korean memory customers. Yield improvements of 1%-4% are possible using rigorous dry edge strip, he said, adding that a 3-4 chamber cluster of these edge strippers may see production.

Lam quietly released this tool in 1Q07, and now claims to be engaged with 18 of the top 25 capital spenders. “Most of our customers today are in evaluation phases, looking at the yield benefits, and the applications first to use it, but the pull is very strong,” said Gottscho. He said that chamber throughputs are close to what you’d expect from a stripper dealing with low-k etch processes.

Both Novellus and Lam have released useful tools for high-volume production, and both use a hardware shield to protect wafer top-sides while stripping films from edges. However, they are inherently different in the plasma hardware. Novellus’ remote generator design is safe and simple and fits into a load-lock without taking up chamber space. Lam’s capacitively coupled plasma ring provides an additional degree of processing freedom with ion bombardment, but requires the space of a process chamber to do so.

Applications-specific hardware solutions such as these are just what the industry needs to maintain productivity while ramping the production of nanometer-node ICs. While the core technologies are not new, they have been combined in new ways based on direct feedback from end-users. The natural evolution of sophisticated hardware continues within the industry ecosystem.

—E.K.

Labels: edge, Lam, Novellus, plasma, silicon, strip, wafer

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070907: Lam & Novellus both strip wafer edges

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Ed’s Threads 070413
Musings by Ed Korczynski on April 13, 2007

MRS meeting specs the future
The Materials Research Society (MRS) spring meeting was in San Francisco April 9-13, and the near- and far-term possibilities for process technology in our industry were presented to a record numbers of attendees. Researchers showed results from the world’s leading labs for electronic materials development: CMOS high-k gate dielectrics, nano-imprint lithography, organic semiconductors, quantum dots, and nano-tubes. It’s like sipping from a firehose, unless you’re interested in just one of the 36 parallel sessions.

Sachin Joshi of UT-Austin showed that hybrid-orientation technology (HOT) silicon wafers based on the MEMC direct silicon bonding (DSB) approach contain inherent defect-rich junctions between orientations. Shallow-trench isolation (STI) regions 60-140nm wide may be used to eliminate these defects, though this seriously limits circuit density, he pointed out. Non-silicon channels will probably also limit density, so their use will probably be limited to RF and mixed-signal applications in small portions of chips.

Arief Budiman from Stanford analyzed the grain orientation in submicron damascene copper lines using the synchrotron x-ray beam from the ALS Berkeley Lab. This very bright x-ray source and submicron spot-size (0.8 x 0.8µm) allows for resolution of crystal bending/stress as well as the dislocation density. Starting with large single grains spanning across the width of the line (“bamboo structure”), Budiman’s group observed clear directionality of EM-induced plasticity and thus the orientation of slip-planes. They found that <112> orientations were most susceptible to plastic deformation, so any grains with such orientations that line up with the induced EM-stress will deform. Grain orientation controls plasticity, which in turn influences EM degradation mechanisms and circuit reliability.

An analysis of the influence of microstructure on void formation in failed copper interconnects, from Intel's Sadasivan Shankar, revealed that voids first nucleate at triple-boundaries caused by stress-induced de-cohesion at copper interfaces. These voids can be easily pinned by a grain boundary, which provides a fast diffusion path for the void to grow across the width of a line or via. “It almost unzips the grain-boundary,” he commented. A 2D model developed with Brown and UT-Austin accounts for current flow and stress, diffusion along surfaces and interfaces, void migration, and the interaction of voids and grain boundaries.

Duane Boning, the MIT professor who created one of the first useful pattern-density step-height CMP models in the 1990s, showed progress on new physically based models. By explicitly including pad properties—elastic response (including lateral coupling across the pad), slurry transport, and average asperities—he showed how chip-scale uniformity can now be predicted.

Roland Rzehak of Qimonda in Dresden, Germany, provided both an overview and details of inexplicable CMP removal-rate variations using ceria-slurries. A counter-intuitive “slow start phenomena” slows the removal rate for the first minute of pattern planarization to be ~2.5X lower than that for blanket films. Ceria particles may initially adsorb in trenches to take some of the pressure load. However, Qimonda observes additional non-uniformities implying influences of pattern pitch, the pad material, and possibly effects from chemical additives to the slurry.

MRS meetings also cover wilder technologies like superconductors, neuro-prosthetic interfaces, and “the nature of design using nature’s portfolio” like the self-assembly of sea-shells or the nano-hairs of gecko feet. Materials scientists and engineers continue to explore the structure-property relationships of the physical world, and confirm that there is indeed “still plenty of room at the bottom.”

— E.K.

Labels: electronics, materials research, modeling, nano, self-assembly, silicon

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070413: MRS meeting specs the future

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