Ed’s Threads 080602
Musings by Ed Korczynski on June 2, 2008

IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) were discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes (CNT) along with new copper barrier materials.

3D with TSV may be considered as the ultimate interconnect concept, since stacked chips provide optimal functionality/volume, and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV and the many variations thereof have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, “via-first” TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, “3D is such a ‘silicon-centric’ process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here.”

Fraunhofer IZM (Institute for Reliability and Microintegration) in Munich has been leading the world in 3D-IC work for over ten years, and researchers from there have been developing detailed system-level heterogeneous integration schemes for wireless applications (for the European 3D integrated sensor program “e-CUBES”). Their target is die-to-wafer (D2W) stacking of a tire pressure monitoring system (TPMS). The wafer has the microcontroller chips, onto which are stacked chips for the RF transceiver, pressure sensor, and bulk acoustic resonator (BAR). For TSV, they integrate chips with both solid metal trenches (typically W filled ~20 µm deep) or hollow vias coated with doped poly-silicon (through the 300 µm thick pressure sensor).

Researchers from Georgia Tech built upon work they first showed three years ago at IITC, and together with IBM and Nanonexus showed real results of using integrated microchannel cooling to remove heat from 3D-IC stacks. Fluidic microchannels were fabricated at the wafer-level using four lithography steps, and the resulting chips showed thermal resistance of just 0.24°C/W compared to 0.6°C/W for equivalent 65nm node air-cooled chips. With reduced thermal resistance, significant advances in speed, power, and/or operating temperature can be achieved; for example, power could be reduced ~20% at the same frequency, or the frequency could increase 10% at the same power.

Basic materials integration challenges of 3D integration were shown in two presentations by IMEC. Micro-Raman spectroscopy (µRS) was used to determine the plastic yield criterion for an accurate finite element modeling (FEM) of the stress near Cu-filled TSV. Due to the inherent mismatch between CTE of Cu (16.7 ppm/°C) and Si (2.3 ppm/°C), some strain will be inherent, and it may degrade electrical carrier mobility. Defining an “exclusion zone” of transistors from the TSV such that mobility degrades <5%,>
IMEC researchers also looked at reliability in a presentation on “Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking.” Both Cu-Sn and Co-Sn were shown to withstand 1000 hours of testing at the extremely aggressive conditions of 150°C and 0.63mA/µm2).

Scott Pozder of Freescale Semiconductor showed an excellent poster on Cu-Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding of flipped dice on a wafer. After D2W bonding using Cookson F602 material at micropad pitches of 59, 64, and 69µm, the robustness of the bond was shown by grinding the bonded dice to 50µm thin using a Disco Hi-Tec tool. While no TSV are used in this die-to-wafer stack, this pragmatic approach based on standard unit-processes which can be found in the open foundry market shows one clear way forward toward 3D today.

Tohoku University researchers showed one way to cut costs in D2W bonding: use a rough lithographic step to form hydrophobic and hydrophilic areas on the wafer, add an aqueous coating and then roughly place the dice. The surface tension of the liquid induces the dice to self-align, and control of the ambient can allow for the liquid to evaporate which temporarily bonds the dice to the wafer. The average alignment accuracy on 100 dice was ~0.5µm, with most dice aligned within <1µm and all <1.5µm.

D2W stacking of 3D chips allows for the used of known good dice (KGD) and the associated minimization of yield losses anticipated with wafer-to-wafer (W2W) stacking. D2W stacking technology will first follow Freescale’s lead by flipping the top die for two levels of silicon, but TSV and three or more levels will certain follow.

Much of the limitation in the use of TSV today remains with the designers; lacking EDA tools, it is not only difficult to optimize a design for 3D, it is challenging to just try to quantify the potential benefits in advance. Until EDA tools are ready the greatest potential value of 3D stacking will not be seen, and most commercial TSV will continue to be used for memory stacks and CMOS image sensors.

This is the last year in which interconnect technologists living in the San Francisco bay area have the exclusive luxury of the International Interconnect Technology Conference being local. Next year (June 1-3, 2009), the 12th IITC will occur in Sapporo, Japan at the Royton Sapporo hotel. The 2010 meeting will be back in the San Francisco bay area, and then the 2011 meeting is expected to occur somewhere in Europe.

—E.K.

Labels: 3D, IITC, interconnect, silicon, stack, through-silicon via, TSV

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080602: IITC shows the way to 3D

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Ed’s Threads 070928
Musings by Ed Korczynski on September 28, 2007

Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).

Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.

Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.

TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.

These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.

Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.

Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”

Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”

All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.

While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.

--E.K.

Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via

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070928: Who needs through-silicon vias?

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