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080225: Interconnect technology mature
Ed’s Threads 080225
Musings by Ed Korczynski on February 25, 2008

Interconnect technology mature
On-chip interconnects made primarily of copper metal insulated with SiOC low-k dielectric material are the current state-of-the-art for the commercial IC manufacturing industry. A report from the TECHCET Group quantifies the materials that are forecasted to be needed to form interconnects for 65nm to 32nm node ICs. Except for some new barrier layers, the only major change on the interconnect horizon is the use of pores or air-gaps in the dielectric material to get to ultra low-k (ULK, a.k.a. extreme low-k or ELK).

Though carbon nano-tubes (CNT) have been considered as new conductors, and self-assembled dielectrics have also been investigated, commercial IC fabs are necessarily slow to change proven technologies, and so it is almost certain that these newer approaches will not be used for commercial IC manufacturing anytime soon.

From first principles and reasonable modeling, we know that Cu is not the ultimate electrical conductor, but lacking room-temperature superconductors and ways to form dense arrays of metallic CNTs, the only near-term solution is to use more and more copper layers as a method of dealing with higher resistance copper in smaller lines. With Cu pushed to the limits, it is axiomatic that current density inside minimum pitch lines is huge such that electromigration induced reliability problems are inherent.

Cu lines in advanced dual-damascene interconnects are already complex structures, with barrier layers to prevent Cu diffusion into low-k dielectrics. An ideal Cu barrier inhibits electromigration, though any barrier is more resistive than the Cu itself, so it should be as thin as possible to minimize resistivity without allowing for Cu diffusion. For the 32nm node, Copper Manganese (CuMn) and Ruthenium barriers have been investigated, in part due to the integration advantage of being able to electro-plate Cu directly on either barrier without the need for a PVD Cu “seed” deposition. If CuMn is used, then some of the Mn diffuses to the surface of the Cu during metal anneal, and removing this surface Mn during the CMP step results in lower via resistance due to a direct Cu-to-Cu bond.

For cap layers, silicon nitride has been used at ≥90 nm, but it has a rather high dielectric constant of ~7, so SiCN with a dielectric constant of ~5 has been used at 65nm. For 32nm the most likely capping barrier may be CuSiN—formed by reacting the post-CMP Cu with SiH4 and NH3—or CoWP.

Dielectrics technology has never met the wishes of the ITRS for a different material for each node. With the k-value stuck at ~2.7 for a blanket SiOC film, the only practical solution to lower k has been to substitute “air” (a low-pressure vacuum, really) as part of the dielectric material. The air can be in random zero-dimensional “pore” (or nanopore) structures in the material, which may be formed by sublimating the homogeneously-nucleated 2nd-phase of a deposited blanket film. The air can be in random or ordered one-dimensional “air columns” in the material, as shown by Edelstein et al. at IBM. The air can also be in patterned two- and three-dimensional “air-gaps” formed by many different process flows, as shown by Hoofman et al. at Philips/NXP.

Conformal dielectric CVD processes can also be tuned to automatically form air-gaps between lines—known as “key-holes” or “bread-loaves” due to the characteristic shape of the gap when viewed in cross-section—for metal line spaces of a certain pitch. Standard dielectric CVD processes are tuned to avoid air-gaps in random line spaces so that gaps do not appear spontaneously in some portions of a random IC design. Key-hole air-gaps as desired dielectric structures were first reported by Shieh et al. of Stanford in the pages of SST in 1999, and the major limit with their use has been the need to impose design constraints on metal line pitch.

However, it now appears certain that nearly all 32nm node ICs will be made with restricted design rules just so that lithography will work. Likewise, CMP and Etch uniformity specifications at 32nm seem to mandate severe restrictions on geometry and the extensive use of “dummy fill” beyond all precedent. If a design must already deal with such limitations, then why not integrate in key-hole air-gaps by CVD? Alternatively, like IBM or Matsushita, you can use a non-critical lithography masking step and etching to define the air-gap locations independent of line pitch.

Lest we forget, aluminum metal is still used as the on-chip interconnect for some 65nm node memory chips. Proven process technology is replaced only when IC performance mandates a change, and so evolutions happens far more often than revolutions.


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080225: Interconnect technology mature

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.