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070525: Intel-IBM fab hype-war and truths
Ed’s Threads 070525
Musings by Ed Korczynski on May 25, 2007

Intel-IBM fab hype-war and truths
It has been said that the first casualty of war is the truth…even more so in a hype-war. An interview appearing on a popular electronics industry Web site is the most recent battlefield in this ongoing hype-war between the world’s semiconductor manufacturing heavyweights. As tradeoffs in fab technology become more fundamental at 45nm nodes and beyond, different companies choose to deploy similar technologies in different ways. The truth is inherently complex and thus a bit complex to describe, and can die under the assault of hype.

Among fundamental choices today we find the following: double-patterned dry or single-patterned wet lithography for critical layer patterning, and use of porous or airgap low-k dielectric for on-chip multi-level interconnects. Intel has chosen double-patterned dry lithography and non-airgap low-k dielectrics. IBM has chosen single-patterned wet-lithography and airgap dielectrics.

As shown by Hoofman,, in the pages of SST last year, there are many different airgap process flows, which can produce many different airgap structures. Airgaps may be complete or partial between lines, and this is one of the more fundamental parameters to consider in integrating the structures into real chips. Thus, airgap1 is not airgap2 (General Semantics suggests the use of “indexing” to remind us of the essential distinctions between members of any conceptual set).

Using “complete airgap” flows and removing all dielectric between lines to achieve the absolute minimum capacitance does indeed create the two general problems articulated by Mark Bohr in the recorded interview: an expensive critical-lithography mask to ensure proper via landings, and copper electromigration sensitivity. However, the IBM flow uses airgaps only in the middle of line spaces while leaving dielectric material on the sidewalls of copper lines.

The IBM airgap process exposes parts of some metal sidewalls during the tricky three-stage gap etch, but the subsequent dielectric CVD process re-coats the exposed sidewall areas prior to “pinching off” the tops of gaps. With adequate sidewall dielectric in place, via landing and electromigration issues can be minimized if not avoided. Intel’s Bohr certainly understands airgap integration issues far better than I do, but because he’s not in a position to comment on how his competitor’s process might work, he accurately and properly expressed Intel’s results in the interview, and the generic disadvantages of approaches not currently taken by Intel.

However, a statement summarizing the interview reads thusly: “Mark Bohr, Intel senior fellow, says his company looked at air-gap technology like IBM recently introduced, and dismissed it as costly and inefficient.” That's a misinterpretation. The truth is that Intel never panned IBM’s airgap technology—Bohr answered a specific question about IBM’s technology with a generic answer about non-IBM technology. Of course, Bohr can very reasonably say that he has no knowledge if IBM’s technology beyond what is muddied in the official press release. Since IBM’s marketing spun the technology truth to the point of grandiose hype, it provides easy opportunity for Intel to comment on the hype instead of the truth. (Incidentally, further information on the general concept of self-assembled nanotechnology for lithographic masking applications can be found in the most recent issue of Microlithography World.)

The IBM hype was that no new lithography is needed. Intel counters that a generic process flow for airgaps requires critical-lithography steps. The truth is that the IBM flow does use an additional lithography step for each airgap level, but it’s non-critical and the mask generation has been automated as a button in the EDA deck. Critical-lithography steps for 45nm node processing can be 10X more expensive than non-critical patterning steps. If the IBM airgap process required critical lithography for each level then it might add 20%-25% to the cost of each chip, but with non-critical lithography it might add only 5%-8%.

For most people in the world who lack experience in fab processes, subtle complexities get lost in translation and details are distorted or lost. The truth about nanometer-era fab processes is that they are all tough to develop with inherent integration trade-offs. With Intel and IBM now going down divergent paths, it’s truly difficult to assess a fab technology “leader” in anything but hype.

— E.K.

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070525: Intel-IBM fab hype-war and truths

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Anonymous Dan Edelstein said...

We (IBM) have been wrongly portrayed as having chosen a different path, i.e. of airgaps instead of low-k or ultralow-k, and that we have “diverged.” (also wrong in implied added cost, mask/litho needs and criticality, and other pot-shots). In fact we were quite surprised at this misinterpretation - that concept was never stated by us nor meant to be implied. It's especially surprising given all the leading low-k and ultralow-k progress we have published and put into production. We are simply adding airgaps to our arsenal - as an option on top of a low-k baseline technology - not at the expense of the low-k insulator used in the baseline build to be gapped. Also please note there is no comparison between the wiring capacitances. Our airgap approach drops any given wiring capacitance by ~35%, regardless of how low the "k". Most chips would not require all levels to be gapped, if any. We think our high-end server CPU's will benefit the most.
For references on our leading low-k roadmap (which is lower-k than Intel's at each node), please refer to our 45-nm announcement at IEDM 2006, and prior papers on 90-nm and 65-nm at IITC 2004, IITC 2005, and AMC 2006. We are continuing our low-k reduction path, as our alliance partners, vendors, and customers know. We intend to keep pushing along the leading edge of low-k BEOL, and that in turn is underpinned by noteworthy experience developing those low-k materials, as well as understanding root causes for Cu reliability.
Airgaps are positioned on top of that baseline, reducing k by ~35% for just ~1% additional wafer cost per level gapped (and yes indeed, the added lithography is noncritical, and we didn't hold back in specifying that - it appeared in your first article, as well as Microprocessor Report May 21 and several others who published our process flow).
So to sum up, our airgap approach is a low-cost/high-performance option, selectable by chip and by wiring level, and fabricated on a competitive low-k BEOL baseline. The issue is not either/or, i.e. either gaps or low-k. It is simply whether one has this gapped option to offer, or not.

Tue Jun 12, 06:38:00 PM PDT  

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070511: India scripts future for Fab City
Ed’s Threads 070511
Musings by Ed Korczynski on May 11, 2007

India scripts future for Fab City
As I recently wrote in this blog space (see “Turn-key fabs for India”, April 6, 2007), India may soon be joining the world of “fab-ulous” nations. On May 10, “Dr. YSR” Reddy, Chief Minister of the government of Andhra Pradesh (GoAP), and a delegation of IT ministers and advisors were in Silicon Valley to meet the actor governor of California,
and also to promote their state as a place for high-tech investment. Andhra Pradesh (AP) claims an information technology (IT) growth rate of 50%-55%, the lowest electricity cost in India, and good water resources.

In particular, Hyderabad boasts of a new international airport to be operational by March 2008, an eight-lane outer-ring road and a metro-rail transport system also being built. “With our resources—which are better than many states in the country—we will support the first fabs in India.” said Reddy. “We want to make the infrastructure world-class, and this is being worked out now.”

Dr. C.S. Rao, IT advisor for GoAP, provided additional details of the infrastructure priorities. AP has been very successful in pharmaceutical manufacturing, so there is confidence in the same result for semiconductor manufacturing. “GoAP believes strongly that chip manufacturing in AP will generate hundreds of thousands of direct and indirect jobs in AP, and this is one of the reasons it is a very high priority for us,” informed Rao. “These are very exciting times for AP to get in on the ground floor of this opportunity and become a leader in India.”

A semiconductor fab requires uninterrupted electricity and water to properly function, and the GoAP understands that supply of these resources will be critical. “GoAP is simultaneously prioritizing the rural sector and the manufacturing sector in AP,” explained Rao. “Therefore the best way to meet these priorities is not sacrifice one for the other but instead have enough supply of water, power, land, etc. so that these priorities can be met simultaneously.”GoAP has issued orders that 10% of water in all irrigation projects in the State should be reserved for industrial uses, but there are many active and developing industries in addition to the Fab city project in Maheswaram in Ranga Reddy. A short list includes: two IT parks, one IT Special Economic Zone (SEZ), one hardware SEZ, one IT industrial park, and a gems and jewelry park.

Despite conflicting requirements for basic resources, the government seems to have set proper priorities to establish semiconductor fabs. GoAP has already committed to installing by the end of this year a pipeline capable of carrying dedicated capacity of 20 million gallons of water/day for multiple fabs and other manufacturing in Fab City. "This pipeline is already started to be laid out and will be done,” said Rao. “There is no conflict here.”

Regarding the electric power, up to 200 MW of power is being made available for Fab City with two different grid lines. “Again, the commitment by the government of Andhra Pradesh is total and comprehensive,” said Rao, noting that the government of AP will be minor partners in projects spanning the 1200 acres of Fab City. Though 200 MW is a great amount of power, it will be easily consumed by a handful of fabs and supporting businesses.

A typical 200mm fab with 20,000 wafer starts/month (WSPM) fab consumes ~130 kWh/yr of electricity, according to a World Wide Fab Energy Survey Report published by International SEMATECH (Technology Transfer # 99023669B-ENG, June 30, 1999). Assuming steady consumption, average 200mm fabs thus need ~17 MW of electricity to run. Applying the 1.5x rule for 300mm tool scaling, most 300mm fabs would consume (1.5 x 17) ~25 MW for 20,000 WSPM; however, since most 300mm fabs are scaled to >30,000 WSPM their typical power needs scale proportionally to >38 MW continuous power.

It looks like the first commercial chip-making facility in FabCity will be a SEMindia test and assembly line (i.e., “die-based final manufacturing”) supposedly breaking ground within weeks. Test and assembly lines typically don’t consume nearly as much power and water as IC fabs (i.e., “wafer-based manufacturing”) and they are really quite different manufacturing environments, though still part of the “chip-making ecosystem.” SEMindia still plans to eventually startup an IC fab in Fab City, but a start date is currently tentative since partner AMD has slowed capex spending.

The first IC fab in Fab City is supposedly again going to be that of Nano-Tech Silicon India Ltd. (NTSI), a start-up led by South Korean businessman/technologist Dr. Jun Min. NTSI has been trying to close financing for at least two years, and though the company had at one point claimed Intel Capital was an investor, as of today no official relationship seems to exist between the two. Rao told WaferNEWS that Min is “doubly confidant that he will be able to have financial closures with prospective investors in the next 90 days” -- but the basic structure of the project has been scaled down, with phase1 capacity plan reduced from 30,000 WSPM to 20,000 WSPM. An entire used 200mm tool set can be acquired for <$50 million these days, so maybe the NTSI project will now finally move forward.

Many details remain to be resolved with specific projects, but at least the government seems to have a clear policy of support for fabs, and it now seems to be a race to first silicon. Will NTSI get its financing together in time? Will HSMC and Infineon get its turn-key fab up and running first? Will SEMindia and AMD find money for a fab? One way or the other, it now looks like Fab City in Hyderabad in Andhra Pradesh should be producing ICs on silicon wafers within two years.


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070511: India scripts future for Fab City

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Anonymous Anonymous said...

so far nothing happened. no electrical infrastructure and no water pipes. government is only fooling to promote the nerby real estate ventures.

Fri Nov 09, 06:52:00 PM PST  

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070504: IBM add airgaps for faster chips
Ed’s Threads 070504
Musings by Ed Korczynski on May 04, 2007 (updated June 12, 2007 to correct details of the IBM airgap etch process, which had erroneously referred to the third-step being RIE, when it is wet as confirmed by both D. Edelstein and S. Nitta)

IBM adds airgaps for faster chips
Airgaps have long been considered as structures to increase the speed of on-chip IC interconnects, though no one had developed manufacturing-worthy process flows. Only in the last year have companies such as Philips (now NXP) shown overviews of likely airgap manufacturing processes, though without production commitments. Now IBM has invented a new variation on airgaps that uses a self-assembling polymer mask layer as part of the process flow, and claims this can be a simple drop-in addition that adds only ~1% to chip cost for each dielectric layer gapped. Thus for an advanced multilevel interconnect, a ~5% cost adder should provide 35% faster chips or 15% less power consumption.

Circuit speeds are limited by the dielectric constant (k) of the insulating material surrounding metal lines, so the industry's Roadmap has focused on ever lower k dielectric materials. Unfortunately, materials engineering for a new dielectric material is difficult and expensive, and despite tremendous efforts and many false-starts over the years, the entire world has now settled on SiCOH by CVD as the lone dielectric material (k~3) that provides acceptable cost, yield, and reliability. So-called ultralow-k (ULK, aka “extreme low-k”) films are merely k~3 SiCOH with the addition of ~20%-40% by volume of nanopores to reach k~2.4. More nanopores cannot be added without degrading yield and reliability, so the only practical way to get to k~2 is to incorporate a single large pore with clever processing as an “airgap.”

A multiyear development effort to create a manufacturable airgap process was led by IBM fellow Dan Edelstein, program manager for low-k CVD BEOL, who provided Solid State Technology and WaferNews with exclusive insight into how they achieved these remarkable results. He explained that unlike previously known airgap process flows, the IBM approach starts with a standard dual-damascene copper and SiCOH dielectric process that has been in production for years. Airgaps are formed using a multi-step etch, using a hardmask patterned with either self-assembling monolayers or standard lithography depending upon the geometry of the interconnect.

Unfortunately, IBM's press release touting the airgap achievement is so grossly hyped that it’s caused severe misunderstanding throughout most press reports on this process. The new technique "skips the masking and light-etching process,” says the official release. “Instead IBM scientists discovered the right mix of compounds, which they pour onto a silicon wafer with the wired chip patterns, then bake it.”

In reality, while self-assembly can be used to make an array of nominally 20nm holes by spin-coating and baking, these holes merely pattern the hardmask that is used to etch the gaps into the dielectric, explained Edelstein. A non-critical lithography step is used to block out circuit areas that do not need gaps, he said. The self-assembly layer is not even used to pattern the hardmask used to make airgaps at upper levels of the interconnect. “At some point in the hierarchy it becomes more viable to use lithography instead of self-assembly,” he said.

While IBM doesn't use airgaps for the first level of metal, they could be used at any of the higher levels within the hierarchical interconnect stack, Edelstein noted. “Most chips won’t need air-gaps on all levels, but perhaps on half,” he said.

No matter the level, a special three-step etch process to form gaps with narrow top openings is the key to this process (see figure). “We etch a narrow channel down so it will cap off, then deliberately damage the dielectric and etch it so it looks like a balloon,” he explained. “You have a big gap with a drop in capacitance and then a small slot that gets pinched off.”

Starting with dual-damascene copper lines/vias and SiCOH single-phase dielectric, the essential IBM airgap process flow is as follows:

1) Deposit hardmask;
2) Spin-coat an imaging layer; either special new diblock polymer or standard photoresist;
3) Create holes using either the self-assembly properties of the diblock or standard lithography;
4) Block out circuit areas to not be etched using non-critical photolithography;
5) Transfer holes from the imaging layer to the hardmask;
6) Etch three-step sequence—first an anisotropic RIE to form deep openings into SiCOH, then plasma damage of the column sidewalls, then isotropic wet etch to remove most of the remaining SiCOH underneath the hardmask;
7) Strip hardmask; and
8) PECVD of the next SiCOH dielectric level to cap the gaps with a classic “pinch-off” shape.

Since the self-assembling mask layer is not aligned to the underlying interconnect structures, and since the block-out mask is “non-critical” to save costs, the hardmask will inevitably expose the tops and sides of some metal lines to RIE. Consequently, the SiCOH etch chemistry needs to have excellent selectivity so as to not attack copper and any metallic barrier layers. Edelstein says that they’ve been able to work with standard gas precursors for this critical RIE step.

The new airgap process is an optional loop off of the standard flow, so designers can choose to use airgaps at any of the levels in the on-chip interconnect hierarchy—and IBM also has developed an automated algorithm for making the block-out mask. “As a customer you can turn on the air-gap option for any level on any chip. We can put the gaps in independent of any incoming design,” Edelstein told WaferNEWS. The ability to add air-gaps as a “drop-in” to an existing on-chip interconnect process flow minimizes risks, and explains the company’s confidence that this flow will be used in manufacturing by 2009.

While the diblock polymer is only one part of this airgap process, it is a significant addition. Chemists at IBM Almaden Research reportedly developed this material for broad applications in fabs—it’s like a standard photoresist in terms of handling and dispensing, it has a wide process window, and IBM has detected no shelf-life problems for up to one year.

Using self-assembly in coordination with lithography opens up new possibilities in general for integrated process flows, so look for news of additional applications in coming years. “We hope that we can use directed self-assembly to get to other device features,” said Edelstein. “This is just the tip of the iceberg.”

— E.K.

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070427: Life after CMOS commoditization
Ed’s Threads 070427
Musings by Ed Korczynski on April 27, 2007

Planning for life after CMOS
It’s hard to feel upbeat about the future of mainstream semiconductor manufacturing after attending this year’s SEMI Strategic Business Conference in Napa, CA, where presentations detailed the end of the good times. After decades of leading the world in high-tech value-adding, the IC business is now mature and just another part of the global electronics industry. This is nice enough, unless you remember the record revenues, profits, and capital equipment expenditure levels of the 1990s.

Trends within the IC industry indicate that the average cost to develop a new IC product has risen from $10M at the 90nm node to $50M at 65nm. With a targeted 10x return on research and devleopment over the life of the product, you need to see over $500M in chip sales for a single 65nm product. Remembering that consumer chips typically sell for $5 each in quantity, that means before even starting a new 65nm chip design you need to show demand for 100M units, which will effectively lock out a number of applications spaces, noted Wil Josquin, VP of strategy and innovation for NXP Semiconductors.

In his concluding keynote presentation, Art Zafiropoulo, CEO of Ultratech, included a slide from Freescale showing the percent of investment into a final IC product going toward packaging has gone from <20%>50% in the last five years. His final slide ended with the final line reading that advanced packaging will be the only differentiating technology. Amkor’s David Hays, VP of business development, wafer level processing, reminded the audience that, “There’s no way to get all the features and functions in cell phones that we all want using old chips and old packages.” For example, Motorola’s trend-setting V3 RaZR handset includes six chip-scale packages (CSP) plus 14 wafer-level packages (WLP).

Despite providing substantial value, outsourced semiconductor assembly and test (OSAT) providers such as Amkor or STATS/ChipPac find it difficult to make a profit. “The industry doesn’t want to pay us to do the work we do,” Hays lamented. “It’s like Walmart -- they’ll say what they’re willing to pay for it, and it’s up to you to figure out a way to make a profit.” There are seemingly no more obvious and easy solutions available. If you do a silicon chip shrink from 90nm to 65nm nodes for cost savings, you may find that the added packaging cost to handle a smaller chip with tighter pitches negates any saving in the silicon.

Consumerization drives rapid electronic product life cycles that stress the supply chain. Scott DeBoer, Micron’s director of process development, reminds us that commodity pricing can be very volatile —e.g., NAND flash spot prices averaged $9.50 on Dec. 1, but had sunk to $5.15 by Jan. 26. Extremely tight coordination is required between EDA, IP, fab, packaging, and ATE partners to have any hope of first silicon right. Plus, after decades of evolution, nanometer-scale CMOS logic technology has reached commoditization, such that the chip itself just doesn’t make the product any longer. Future added-value will come from software and advanced packages and bundled-internet-subscriber-services, not from the ICs which power it all.

With Intel sending 90nm logic technology to China, and TI stopping CMOS development at 45nm, the writing is clearly on the wall. Mike Thompson, manufacturing operations GM for STMicroelectronics, did the math for why TI said no more, concluding that process technology spending as a % of development is being squeezed out by increasing efforts in software development for new products in the ASIC/ASSP world. With ~$400M required to develop a new silicon process technology, if this is 20% of the total research and development budget which is capped at 20% of total sales, then only IDMs with >$10B IC revenue can maintain independence in silicon process technology development. For logic technology, the world is settling down to just three or four independent sources of mainstream CMOS technology development: Intel, the IBM ecosystem, the foundries, and Japan.

IBM continues to lead the industry in technology innovation as the center of the collection of partners in the Common Platform Alliance (CPA). This alliance includes many design and packaging members who add value beyond the limits of silicon, such as Amkor, ARM, Analog Bits, Blaze, Chipidea, Clear Shape, Cadence, Magma, Mentor Graphics, Ponte, Synopsys, and Virage Logic. The industry continues to innovate using current business models, though we should expect to see many shake ups below the first-tier of IDMs, OEMs, and OSATs.

Major IDMs will continue to manufacture in-house, though they will both provide and use more and more foundry services. Fabless companies will continue to function as they have in recent years, with clear distinctions between the top-tier and all others. Medium-size IDMs will partner to remain “fast-followers.” If you’re supplying equipment or materials to leading-edge fabs, expect that greater purchasing power will consolidate into fewer hands. Overall what can we expect from the new reality of CMOS logic commoditization? Keep up the good work, and you might even get paid some day.

— E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.