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070622: Intel researches teraflops and biochips
Ed’s Threads 070622
Musings by Ed Korczynski on June 22, 2007

Intel researches teraflops and biochips
Andrew Chien, Intel VP and director of research, provided an exclusive interview with Solid State Technology and WaferNEWS during Intel Research Day this year. Chien heads all Intel research, involving nearly 1000 people at 15 locations worldwide (three of which are at universities). “There are nearly a hundred people doing research, and nearly a thousand people doing platforms based on the research,” explained Chien. “It’s not device physics or materials science, it’s real manufacturing work.” You can now find more information at [email protected] Blog.

Chien is responsible for thinking of new microprocessors, new microprocessor applications (including those embedded), and novel fab-able devices that could retain high profit margins. Discussing novel non-silicon transistor technologies, such as printable or polymer electronics, Chien expressed that these newer technologies must find winning applications beyond what is currently served by silicon chips.

Opportunities exist in the intersection of digital CMOS fabrication technology and biological applications. Intel's Fab8 in Israel has been working on novel sensor architectures based on field-effect devices on 200mm wafers, where the quantity of specific molecules bonded to uniquely tuned sites creates a change in current flow. Think of this as similar to sticking a sensor layer to the top gate of a FET where the change in bonded molecules alters the current flow through the channel. Integration of sensor elements with CMOS circuitry in a hybrid-SoC is expected to be easily done on-chip; while sensors could be integrated with separate CMOS chips in 3D stacks, there is already sufficient “free silicon real estate” at the periphery of the sensor areas to fit in all the CMOS needed.

Intel is also trying a super-computer architecture end-run on IBM’s Blue Gene, by releasing a Teraflop multicore single chip. On display at the Research Day event was a rack with a board stuffed with very fancy metal packaging and active water-cooling loops surrounding a (reportedly) 275mm2 160-core chip in 65nm technology. This chip has been shown to perform at 1.01 teraflops @ 0.95V, 62W based on the following single-chip architecture:
1 poly, 8 Cu metal lines form a 2D mesh,
100 million transistors with dynamic power management,
80 tiles (3mm2 each) composed of dual FPMAC cores, and
Packaged with 1248 pins (343 signal) C4 and a 14 layer PCB.
Memory hierarchy for this new chip design includes private L1 memory within each core, as well as several levels of shared L2 cache. A third level of SRAM or DRAM cells will likely be integrated as a separate chip in a 3D stack to manage bandwidth requirement in integration to the overall system.

What a bunch of teraflop chips is very good at is anything “computationally intensive,” requiring extreme amounts of computing power -- for example, calculating the interacting and overlapping phases of light shifted by randomly placed sub-wavelength features across a vast 2D space, a.k.a. inverse-lithography maskmaking (see related writeup by phase-shift mask pioneer and MicroLithography World editor M. David Levenson). Yan Borodovsky and Vivek Singh showed a mask with pits etched to greater depth for longer wavelength red, so that a common laser-pointer shone through the mask would form a bit of an Intel logo on the wall. You almost have to see this hologram-like effect to believe it yourself. There is no metal to mask the light, just the phase cancellation from the pits. The fundamental capability of computationally intensive inverse lithography modeling will be key to all of Intel’s design- for manufacturing (DFM) going forward, even if the phase-pit masks enabled by the technology aren’t anticipated until <32nm.

Beyond manufacturing, Intel also researches software breakthroughs that might demand a lot of processing power. “We shifted resources to respond to the increased focus upon ‘context-dependent computing,’ where sensor data is processed to determine whether you’re eating, sleeping, or watching a performance,” explained Chien. “We can already determine human emotion based on facial gestures, and that information will be incorporated into context-dependent devices.”

With a teraflop possible from a single chip, the capabilities seem nearly endless. Ten years ago, Gordon Moore foresaw that once the atomic limits of manufacturing are reached (still a bit off, but now quite on the horizon), we’ll be in a realm of hundreds of millions of really inexpensive transistors, and clever designs will break open whole new applications for silicon chips. Chien confirms that the design mindset today does not consider the number of transistors to be a constraint, merely the inherent power consumption of those working and waiting. With clock-rates now somewhat fixed, Chien says that it’s actually much easier to work with innovation at the architectural level.

Hold on to your hats, folks—now that designer have to do more than just scaling and clock-accelerations to get performance increases, they might actually start pulling their own weight, and this industry will really take off!

—E.K.

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070615: IBM HK+MG gate-first processing
Ed’s Threads 070615
Musings by Ed Korczynski on June 15, 2007

IBM HK+MG gate-first processing
At the VLSI Symposium on June 14th, and after months of a mainstream press hype-war with Intel, IBM finally unveiled some of the details of its new high-k/metal-gate (HK+MG) transistor technology. Mukesh Khare, IBM project manager for high-k/metal-gate development, presented integration details of the new transistors while keeping specifics of materials and processing confidential. The key information is that their HK+MG “gate first” approach keeps the same processing sequence used by traditional SiON gates, allowing for both technologies to be run on the same line and minimizing integration costs.

“We did a lot of work to look at gate-first and gate-last, and both approaches have challenges,” explained Khare, in an exclusive interview with SST and WaferNEWS. “We picked the approach that is simple, scalable, and also migrate-able.”

Gate-first is simple in terms of changes to existing processes, and looks scalable to smaller device geometries. “Migrate-able” means making it easy to port designs from SiON transistors. Indeed, gate-first processing seems to be the best overall approach -- if you can find a material that can withstand the high temperatures used in device annealing. Keeping most of the existing process flow intact, 45nm will still use tungsten plugs for contacts.

Transistor formation typically requires ~1000°C annealing to allow atoms to settle into proper places after ion-implantation, which inherently damages silicon crystals. Any gate materials in place during annealing must withstand such temperatures without losing their properties. In particular, the high-k dielectric material must maintain a certain composition and material phase to ensure that the transistors do not leak current.

All IBM will officially say to date is that its gate-first high-k material is hafnium-based, which is the currently known default standard, but they will not yet specify anything else. The material is likely to be a blend of hafnium, silicon, oxygen, and nitrogen, which can be seen as just adding the hafnium to the SiON currently used. Hafnium atoms have a relatively higher oxygen coordination number and are simply larger (atomic number 72, compared to silicon at number 14, and oxygen and nitrogen at 8 and 7, respectively), so adding them to the SiON currently used increases the dielectric constant of the layer based on density functional theory. The thickness of the inversion layer under the gate (Tinv) with conventional oxynitride is typically, at best, 18-19 Å -- IBM’s HK+MG transistors reportedly demonstrate Tinv ~12Å, something achieved, by working for over 10 years on fundamental materials engineering.

Though not needing any fundamentally new metrology techniques, every film will require control. For example, compositional changes with nitrogen depth have already been used with nitrided-oxide gates (SiO:N), so one possibility is a nitrided-hafnium silicate (HfSiO:N). Nearly all the recent HK dielectrics that have been shown for CMOS transistors have been stacks of layers with atomic-level engineering of the interfaces. The specific composition and gradients within the layers are officially secret, but it is highly likely that there is at least one atomic layer of SiO at the bottom.

HK+MG transistors at nanometer-scale nodes are constrained by the same trade-offs between speed and leakage (for HP or LSTP circuits, respectively) as with SiON+poly transistors. Engineering the dielectric stack to be either fastest/leaky or fast/tight for a target HP or LSTP, there’s a single HK gradient-stack and one metal used for both NFET and PFET gates. Poly-silicon tops the metal gates. “After more than three years on the 300mm pilot line, there’s been a lot of learning and we’re on track,” Khare noted.

For planar devices, there are more options in terms of ALD, CVD, or PVD, explained Khare. He claims that the cost to use HK+MG is similar to that needed for any new technique like using a dual-stress liner, and so it adds minimal additional cost to the final wafer, but not all designs will need the performance improvement so some chips at 45nm and 32nm will still use SiON+poly. “It depends on the product needs. It is a very powerful technology. It’s very simple,” stated Khare. “The materials challenge was very high k, and that’s one thing we focused on.”

—E.K.

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070608: IITC2007 airgaps & chip-stacks
Ed’s Threads 070608
Musings by Ed Korczynski on June 08, 2007

IITC 2007: Airgaps & chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC) recently held near the San Francisco airport. Two major new materials was presented—IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric—but most new work involves the same materials combined in clever new ways. Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions.

Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers—regardless of equipment, CVD precursor, or plasma preclean—due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue. With subtle integration challenges such as these, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.”

The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone. The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) uses SiO2 at line-levels and a polymer for the via-levels within the dielectric stack, then HF vapor or wet-etch-chemistries to remove the SiO2. NXP and Dow Chemical showed removal of a thermally degradable polymer (TDP) through a CVD SiOC cap layer to make ~30% airgaps at M2 as part of a keff ~2.5 to hit 32nm node specs.

The Crolles2Alliance also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier (SAB) <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.

NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution too.

Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO4·5H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.

Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D; group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier.

Georgia Tech and U. of New Mexico researchers showed that a 60% increase in the total number of wire levels is sufficient to account for ~5x increase in the resistivity of wires. Careful routing and a logical hierarchy seem to go a long way, but eventually the industry must get serious about 3D ICs using chip-stacks.

Patrick Leduc of CEA-Leti provided an overview of the main challenges to realizing high density 3D ICs: bonding with ±1µm alignment at T<400°C, Si thinning to <15µm, and through-silicon via (TSV) diameters <3µm. Thermal management issues may not be too difficult—assuming each transistor contributes 0.7W to a 50 W/cm2 average—since bulk silicon acts as an efficient heat spreader and the metal lines conduct well.

Freescale’s Scott Pozder explained that EDA software tools may be the current biggest limitation to 3D integration, since standard tools cannot even account for metal levels on multiple chips. If you explicitly design for 3D, then models show that multiplicative yield-losses can be avoided or eliminated.

There were ~480 conference attendees this year (plus several hundred additional folks running evening supplier-seminars and exhibit booths). Among the attendees with whom I enjoyed discussions were (in alphabetical order) Al Bergendahl, Chris Case, Paul Feeney, Terry Francis, Mike Fury, Xiao Hu Liu, Steven Luce, Satya Nitta, Mike Shapiro, and a special appearance by casually retired Mike Thomas.

—E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.