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071026: Soitec catalyzes SOI consortium
Ed’s Threads 071026Musings by Ed Korczynski on 26 October 2007
Soitec catalyzes SOI consortium
Earlier this month after the SEMICON Europa show, Soitec
COO Pascal Mauberger, led me on a tour of the company’s two manufacturing and one R&D lines in Bernin, France across the creek from ST in Crolles. Soitec has taken a bit of a gamble on expanding capacity with a new line in Singapore, just when volumes for SOI wafers have publicly stalled. However, strong technical advantages should result in new demand for engineered substrates, and CEO André-Jacques Auberton-Hervé is now leading an industry consortium to catalyze chip-makers’ adoption of SOI.
The “chateau” built to house Soitec has the classic design element of a bridge over a moat, while the mirrored sides of the building reflect the awesome beauty of the French Alps. Inside the complex is the Class1 ballroom layout of Bernin1, the company’s first fab that is now capable of producing 800K/year on ≤200mm wafers. Connected by a walkway, Bernin2 is the company’s Class10-100 ballroom layout 300mm dedicated line (also 800K/year). An overhead transport was added two years ago to increase output to handle the increased demand for all the latest-generation game consoles and AMD’s microprocessor ramp in Dresden. Though PS3 sales have been weak, Xbox and Wii game platform sales have been strong, and all use SOI chips.
Both Bernin1 and Bernin2, as well as the new 300mm line announced for Singapore, use completely standard industry tools from established OEMs to do the specialty implants and thermal treatments needed for their layer transfer process. Among the setup are TEL furnaces, Applied Materials implanters, EVG bonders (a bit customized at 300mm, instead of the standard 200mm size used in MEMS fabs), Mattson and Applied Materials RTP, and KLA-Tencor metrology tools. Over 1000 Soitec employees are running these lines 24/7 and essentially 365 day/year.
Bernin3, a stone’s throw from Bernin2, was built originally by MEMSCAP as its own fab. Essentially just a shell when it was acquired by Soitec in mid-2006
, it now has three 500 m2 cleanrooms doing R&D on III-V materials such as Nanosmart GaN development, and complex pattern transfers. Transferring already patterned layers (not blanket layers) was work originally started at LETI, spun out as TraciT Technologies and then acquired by Soitec
; the first product was imagers using backside illumination. Bernin3 runs 100mm, 125mm, and 150mm wafers, so the R&D tool set is flexible to handle any of these wafer sizes. If any device captures serious demand, then pilot production could occur with dedicated tools in the (currently empty) fourth space in the fab shell. Including its PicoGiga division's work on MBE epitaxy for GaN
, Soitec has a lot of IP and know-how to bring to the development of high-efficiency and high-brightness LED production.
Soitec keeps only a handful of finished goods inventory on site, since the company is completely integrated into a just-in-time integrated supply-chain. Soitec maintains at least one month’s of inventory at each customer site, maintaining ownership until each wafer enters the IC fab line. Likewise, three suppliers maintain starting wafer inventory at Soitec, only “delivering” the wafers when they enter the SOI production line.
Auberton-Hervé, Soitec CEO and newly elected chairman of the SOI Industry Consortium, is modest about Soitec’s role in bringing the possibility of cost-effective SOI manufacturing to the semiconductor industry over the last decade. “We were a bit of the catalyst, but the demand was from the ecosystem,” he claims. The consortium in current form did grow out of periodic SOI user workshops Soitec had sponsored, and Auberton-Hervé notes that interactions between device researchers during a September 2006 workshop led to the demand for the creation of an open ecosystem.
To be sure, the proprietary IBM-ecosystem has had SOI design-flows, design IP, and appropriately tuned manufacturing processes
for lease for many years. Yet not every company has been willing or able to work with the folks in East Fishkill, NY, and so this new consortium may really open up a new avenue to add value for many companies.
“The value of the consortium is in the ability to accelerate innovation,” said Auberton-Hervé. “We have to be more efficient in how we bring value to the whole food-chain. Roadmaps for cost in each segment will help, but it’s more global than that.” Most people think that finFETs really call for SOI, and both represent huge power-savings for portable battery-powered applications. From first-principles it seems that SOI has advantages for mixed-signal isolation. Embedded memory using ZRAM structures (license to Innovative Silicon
) is also an attractive option.
With Auberton-Hervé committed to “doing well by doing good” in leading this consortium for the industry as well as for his company and shareholders, much more of the industry may end up using SOI. It may help with functional integration at 45nm and beyond, and that may help double battery life for next-generation iPods and e-Phones. SOI and other layer-transfer technologies will almost certainly become increasingly useful as simple x-y scaling inevitably slows, and Mauberger will be coordinating the operations of global Soitec fabs to keep the wafers flowing around the world.
Labels: consortium, IC, semiconductor, SOI, wafer
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071026: Soitec catalyzes SOI consortium
071012: Managing mature fabs
Ed’s Threads 071012Musings by Ed Korczynski on October 12, 2007
Managing mature fabs
Associated with SEMICON Europe 2007, the Fab Manager’s Forum
gathered representatives of Europe’s semiconductor fabs to discuss operations of primarily mature fabs. Michael Lehnert, of Renesas Semiconductor, presented examples of the benefits derived from fault detection besides yield improvement in mature fabs. Renesas Semiconductor Europe Landshut (RSEL)
has a 200mm line with 13-15k wspm running 0.5 to 0.15 µm for MCUs (the line was originally a DRAM line).
Fault Detection and Classification (FDC) is a challenge for a fab running several hundred products, with 10 to 100 parameters/tool resulting in up to 5 GB/day of data. With 300,000 SPC charts and 10 entries per chart, and with the data normally distributed and applied 3-sigma limits with a 0.3% false alarm rate, a fab must handle ~1000 false alarms every day. Manufacturing engineers need to change how they work, spending more time with abstract analyses looking at computer screens, and less time crawling through the fab poking at tools. Monitoring facilities parameters such as gas flows and pressures may provide additional relevant data streams.
FDC improvement in wafer-scrap yield was expected, but an additional benefit has been in engineering productivity, with gathering time reduced and more accurate data. Spare-parts and consumables evaluation is now easier, so there is greater confidence in being able to change to less expensive sources when possible. Greater confidence allows for reduction in sampling frequency and reduces the need for dummy wafers. Better preventative maintenance (PM) planning—for example monitoring the filament current in an implanter—results in reduced consumables costs, equipment uptime, and even turn-around time (TAT) due to greater tool availability.
Dr. Detlef Nagel, Sr. Director Product Engineering, Qimonda Dresden
discussed how to manage APC in worldwide DRAM fabs. Future business requires an evolution from APC to predictive process control (PPC), which will in turn require a revolution in data-mining, multi-variate control, and yield prediction. Technology complexity can be kept under control by generic run-to-run (R2R) controllers and virtual metrology.
Qimonda uses SMIC and Winbond as foundries to balance production, along with their own fabs in Europe, the US, and Malaysia. Fast distribution of knowledge is a problem due to regional cultural differences, and the inherent difference between development and volume fabs. One innovative solution is the use of a network of senior equipment engineering specialists, with individuals responsible for an assigned toolset within some areas of expertise. This worldwide captive network improves equipment throughput and reliability at Qimonda fabs; there is traditional information exchange with the foundry partners but not the expert knowledge.
Peter Schaffler, global yield enhancement manager for TI, talked about yield enhancement in the Freising fab
. It was originally a 3” Bosch fab, and has been continually upgraded to the current level of 0.2µm processing on 200mm wafers; the line runs CMOS/BiCMOS with 20k active reticles used on 400k wafers/year. TI now does tool qualification with product wafers, challenging costs and tool availability. Sampling strategy directly affects your costs: too much wastes expenses, while too little guarantees lost yield. Typical these days is 10-20% of lot starts, but sampling frequency should be determined by the number of lots at risk and the complexity of the mask level, which results in tool-specific dynamic sampling. Or course, an efficient data analysis system is needed to provide macros for data drill-downs using tool, parametric metrology, final electrical test, and other data sets. Proper charting and visualization in an interactive GUI allows new analyses to be done.
Single-wafer tracking allows for the extraction of yield-loss signatures like the wafer number in the lot, first or last wafer effects, and different lots with single wafer excursions. For example, electrical-test data that may originally show no signature can be sorted to obtain a clear clustering of parameters into groups of five wafers, which in turn could point directly at a TEL furnace which was the only toolset running batches of five.
A breakout session on the dynamics of the used equipment market provided a fantastic perspective on the status of the current market. In addition to third-party brokers, OEMs now provide refurbished tools with full one-year warrantees for typically 40-80% of the original selling price. As always, the price is set by markets: the price to acquire the tool, cost to properly refurbish, and the customer demand for the tool. At the high-end of pricing, the used tool is sold with all new tool specs and it may then be considered as almost just another new tool for capacity. If the market forces align in certain ways, even a used 150mm tool may be sold for US$2M.
If you buy through a broker, it is somewhat common to then have to purchase a use license (often for the software) from the OEM. These licenses can range from $10k to $700k for complex tools; and are the single greatest hurdle for customers of 3rd-party brokers. The consensus was that licenses are not unreasonable in principle, but customers really expect to receive some value in terms of software upgrades and service support for their payment. Service-contracts from OEMs certainly minimize the risk of working with used or refurbished tools, regardless of the seller.
Hallway discussions with equipment brokers revealed that they’re tracking a tremendous number of 200mm tools which are planned to be decommissioned over the next 1-2 years. How the industry will absorb these tools remains to be seen, but with SECS/GEM interfaces and modular sub-system designs, it’s likely that most of these tools will remain productive somewhere in the world.
Labels: Europe, fab, mature, OEM, semiconductor, tools
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071012: Managing mature fabs
071005: Fairchild at 50 still milking the cash cow
Ed’s Threads 071005Musings by Ed Korczynski on October 5, 2007Fairchild at 50 still milking the IC cash cowThe 50th anniversary of the founding of Fairchild Semiconductor
was celebrated on October 5th and 6th at the Computer History Museum in Mountain View, California. With
Jay Last also in the audience, and with many call-outs to other Fairchildren living and dead, E. Floyd Kvamme
(Marketing) led a panel discussion of Gordon Moore
(R&D), Wilf Corrigan
(Manufacturing), and Jerry Sanders
(Sales). Marketing has really never gotten any respect in the chip industry (unlike at Apple and some software companies), while the other three domains have combined to create the uniquely chaotic culture that is Silicon Valley.
Why do ICs seem to always get cheaper and do more each year? Why do we send manufacturing jobs to other countries? Why are huge egos rewarded in high-tech industries? It all comes from the trial and error experiences of the people who worked at Fairchild Semiconductor in the first ten years of the company’s existence. Driven by a vision, and fueled by caffeine and alcohol, scientists and engineers created new technologies, new companies, and new ways of doing business.
Fairchild Semiconductor was formed by the famous “traitorous eight”
who quit en masse from Shockley Semiconductor in 1957. Gordon Moore explained, ”Shockley was an unusual personality. Someone said that he could see electrons, but he couldn’t work with people.” After trying to get Shockley replaced, Moore confessed, “We discovered that a bunch of young PhDs didn’t have a good chance to displace a recent Nobel Prize laureate.” After first trying to all get hired by another company, they were eventually convinced that they should just start their own company and found funding with Fairchild Camera and Instrument.
R&D was the foundation for everything at Fairchild Semiconductor. Inventing a new industry takes a lot of work, and new devices, processes, and equipment were designed and deployed regularly; at the peak it was “one new product per week.” With intense commercial competition, as long as something works and is reproducible it just doesn’t matter if you know the theory of why it works. “We had a lot of technology that worked but we didn’t understand why,” admitted Moore. Another initial mystery was why technology transfer from R&D became more difficult as the manufacturing people became more technically competent. Eventually, it was discovered that the manufacturing people thought that they would add value by “improving things,” but generally only changed things for the worse. The logic solution to this problem is the “Copy Exactly!” manufacturing strategy of Intel.
Manufacturing semiconductors has always been technically risky and yet like any manufacturing line it must be controlled with a conservative mindset. Trying to conservatively manage risk results in a sort of unique schizophrenia, and has inadvertently accelerated global technology transfer. Wilf Corrigan explained that when he joined Fairchild in 1968 from Motorola, he was immediately struck by the difference in high-volume assembly strategies. “Motorola was very focused on manufacturing excellence, and had thousands of people making automated tools.” In contrast, Fairchild had thousands of well-trained women earning low-wages in Hong Kong. “Using a global approach to drive costs down was part of the legacy of Fairchild,” said Sanders. Moore commented that Intel’s first assembly line using Asian female manual laborers was faster than the then-state-of-the-art automated IBM assembly line, and could rapidly adjust to handle new wafer sizes and package designs. So “outsourcing” has been part of Silicon Valley almost from the beginning.
Sales has always been the vital third leg for the industry. New IC products can break open entirely new lucrative markets, but it still takes someone to go get the order despite problems with manufacturing volumes. Sanders told the story of selling planar transistor against grown-junction transistors by TI, and winning one aerospace contract by putting lit matches to both and showing that the leakage-current went out-of-spec on the TI chip. Kvamm told of selling glob-top packages that failed so easily with a fingernail flick that they were derisively called “pop-tops.” Moore added, “We sold the rejects from our Hong Kong packaging line as eyes on teddy bears.”
Sanders confessed, “When I started with Fairchild, I was single and had no concept of home life. I’d show up at a sales-guy’s house at 7:30 in the morning on a Saturday to start work.” Sanders seemingly has selling in his genes; after 30 years he’s still trying to sell the original AMD mission statement, and during the panel he couldn’t stop himself from making gratuitous pitches for AMD chips. Still, he typifies the “shooting ahead of the target” mindset of a salesman who knows what his customer will need in advance of formal demand. Huge egos are just par for the course, and Sanders proudly recounts signing off on the claimed largest bar bill in Hilton Hawaii history for a global sales meeting. Getting everyone drunk and happy in a group setting was supposedly the only way to keep egomaniacal individuals working together as a team.
The history of the industry is really just the combined stories of individuals, and nearly every classic Silicon Valley success story starts out with a chapter on gross incompetence of top executives at a soon-to-be-former employer. Fairchild drove out Charlie Spork
to create National Semiconductor in 1966. Sanders commented, “When Charlie Spork resigned I was stunned. I said to him you can’t do this, and Charlie just went off on the incompetent corporate management. Charlie said he just couldn’t work here anymore.” When Robert Noyce was passed over to be the CEO of Fairchild in1968, he decided to leave and took Moore with him to found Intel.
The Fairchildren were smart and worked hard, but timing and luck were also keys to success. “The fact that Fairchild started in the technology areas that were the ones that continued—manufacturing use of diffusion, batch processes—was lucky,” admitted Moore. “If you ask me about Intel, I’d say a lot of luck was involved.” Of three different technology and product directions started upon by Intel, only the silicon-gate MOS process was successful. “If it was much harder we might have run out of money before proving it, and if was much easier then others would have copied it,” said Moore.
Fairchild ultimately infected the area to be known as Silicon Valley with the culture of the engineer/entrepreneur archetype, stock-options, and high R&D spending. When there was still innovation to be done, this resulted in tremendous creativity and technology growth. With the major innovations in silicon IC manufacturing essentially in place by the mid-1970s—with the exceptions of lithography and EDA—the last 25 years have been mostly about milking the technology cash cow.
At the reception, one of the Fairchildren pitched his new chip design to me and wanted to know if I could hook him up with some financing for a start-up. Old habits die hard, and I’ve been infected with the entrepreneurial meme
so I can relate, but I can’t help feeling that the time is past for chip startups. Too many competitors have evolved to fill all market niches, and IC functionality has seemingly reached a point of saturation such that software now adds the incremental value. The future of bold innovation belongs to software startups like Netscape and Google, while IC folks can really only anticipate more milking of the herd of cows already bred by the Fairchildren. Pass the milking stool.
Labels: cow, Fairchild, history, semiconductor, Silicon Valley
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071005: Fairchild at 50 still milking the cash cow
070928: Who needs through-silicon vias?
Ed’s Threads 070928Musings by Ed Korczynski on September 28, 2007Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California
. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).
Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.
Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.
TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias”
for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.
These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable
and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.
Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.
Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal
), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”
Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”
All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer
. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.
While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.
Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via
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070928: Who needs through-silicon vias?
Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.