Ed’s Threads 080613
The last musings in this blog on Friday the 13th of June, 2008

Process integration drives the IC industry
The next 10 years will witness more changes in mainstream manufacturing technology for ICs than in the last 40 years combined. An industry based on “what have you done for me lately” can never rest on its laurels, and so innovation must continue, despite limits in 2D scaling. With rapidly escalating costs projected for 32nm node and smaller digital CMOS manufacturing, it is inevitable that IC companies look to analog, packaging, and heterogeneous integration to add relatively greater value for lower cost and risk. Unique process integration challenges at each fab will drive everything for the next ten years, as shown recently by presentations at the recent International Interconnect Technology Conference IITC., some of which I've already discussed in this blog.

What are the ramifications of all of these subtle changes? With basic “unit-process” building blocks fairly well established, it is likely that the only fundamentally new tools to be developed will be for metrology. The current generation of thin-film, lithography, and thermal processing tools are extremely productive and should continue to be used with modest evolutionary upgrades over the next 10 years. The only exception to this is probably EUV lithography, which is still under development but shows promise.

New integration of old processes can be seen in the evolution of barrier layers for Cu metal in dual-damascene structures. At IITC, Novellus showed that PVD Ti/TiN is the newest Cu barrier to replace Ta -- though Ti is the standard barrier for Al metal lines it was replaced by Ta when the industry first began using Cu lines. Though less expensive than Ta, Ti can react with both fluorine (in FSG dielectric) and Cu and so was not considered to be an acceptable barrier. However, now that FSG has been replaced with SiOC in many fabs, a 5nm thin TiN layer (formed with 50 at% N) capping on Ti stops Cu diffusion. An ultra-thin PVD Ti wetting layer on top of the TiN provides a good surface for ECD fill of Cu.

NEC has targeted high-reliability automobile MCUs, and examined PVD Ti/Ru barrier metal for these applications. After 7 hours at 350°C, Ti diffuses into the Ru, but no Cu diffuses through the Ti. PVD-Ru with (001) orientation can be removed by CMP using conventional slurry for Ta/TaN removal. The Ru barrier achieved 12% lower resistance than the conventional Ta type barrier for 70nm wide Cu lines, while time-dependent dielectric breakdown (TDDB) was unchanged. The Ru/Ti barrier shows 35× longer lifetime (T50) than Ta/TaN. Whatever process is finally developed will run for over 10 years with essentially no changes, as per the supply contracts to the auto industry. I toured NEC Roseville recently and saw old 200mm tools being installed with plans to run for >10 years using ≥150nm node processes.

Low-k air-gaps are also great examples of using old unit-processes in new ways, since CVD oxides (SiOx and SiOC) and spin-on polymers already well developed will be used, while established lithography and etching technologies will complete the integration. EDN's Ron Wilson covered many of the latest air-gap integration details from IITC in his fine blog, but the most important consideration is that no new manufacturing tools are needed to make them happen. Designs may need to be tweaked, and the process integration will be challenging, but this approach is relatively low-risk and may be integrated into older fab lines.

Further proving that “there is no more noise (…there is only signal),” IMEC’s Michele Stucchi at IITC examined the effects of inherent line-edge roughness (LER) and via misalignments on the Efield and electrical breakdown between wires. An enhanced electrical field between adjacent lines is induced by LER-induced reduction in spacing. Compared to a nominal electrical field between lines with zero LER, a probabilistic analysis results in enhancement to the field, which can be a factor >2 in 30nm spaced lines. For wires with 30nm spacing, Efield may be high enough to guarantee at least one bridge in 20μm of line length. For via misalignment of 10nm in standard dual-damascene structures with 30nm spacing, the field enhancement can be a factor >3.

An amazing example of tricky process integration to eliminate variability in lithography was shown by Matthew Breitwisch of IBM, in describing work with Macronyx on phase-change memory (PCM) technology. Ge2Sb2Te5 (GST) was the first material investigated which changes from a high-resistance amorphous structure to a low-resistance crystal at ~170°C. A PCM cell is made up of a variable resistor in series with an access device (which may be a diode, BJT, or FET), and current flux near one million A/cm2 is needed for a few nanoseconds to create the change. To concentrate the current in programming, uniform small pores are achieved using a key-hole (a.k.a., “pinch-off CVD”) process:

- blanket oxide, hardmask and nitride depositions,
- lithography,
- anisotropic etching through the dielectric stack,
- an isotropic oxide etch to create an undercut below the hardmask, and
- conformal polysilicon CVD to form consistent 43nm wide keyholes.

The keyhole widths are controlled by the oxide etch and the poly CVD, and not by the lithography, such that equally sized pores form in the middle of line spaces of varying width…all without any new unit-processes.

With razor-thin process windows and systematic process-design interactions, each fab may have to optimize its own integrated process flow. If each fab runs a unique flow, then a mask-set run on one line will yield very differently on a second line, and this reality may create problems for companies trying dual-sourcing with foundries.

New materials and evolutionary upgrades to old materials will continue to support new integration schemes in fabs, while most of the tools will remain the same. However, OEM applications labs will run non-stop as fabs try new designs-of-experiments (DOE) for new integration schemes. It will be increasingly difficult to get process information out of fabs, since each line will have to be set up with unique tricks and integration schemes. Designers will have to really start innovating, as digital CMOS shrinks no longer guarantee lower cost and higher performance.

There will be many IC types that will probably never be designed at the 32nm node. A friend working on a graphics processing chip explained to me that they needed to go to 65nm to get a speed improvement for their target application, but their modeling shows that additional speed will now provide no user benefit. Going to 45nm adds huge design costs and manufacturing yield risk, and so they now plan to stick to 65nm but work on cost and power optimization in re-design. Their next 65nm chip may use 3D interconnects or integrated passives for improved performance, however, so innovation will continue… just in new directions. Such is the blessing/curse of “living in interesting times.”

Henceforth, my challenges will be elsewhere. This is my last blog post on my last day as a Technical Editor for Solid State Technology magazine; I am resigning to pursue other interests, first of which will be an immediate 8-week sabbatical. When I return, I will probably work for the semiconductor manufacturing industry, in an as-yet undetermined capacity that doubtlessly will be "interesting." I thank PennWell Publishing for years of rewarding employment, and wish the company well. Special thanks to James Montgomery, who diligently and masterfully copy edited most of these 76 postings.

—E.K.

Labels: 32nm, 3D, airgap, CMOS, copper, IITC, integration, interconnect, process, research

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080613: Process integration drives the IC industry

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Ed’s Threads 080602
Musings by Ed Korczynski on June 2, 2008

IITC shows the way to 3D
The 11th International Interconnect Technology Conference (IITC) started today in Burlingame near the San Francisco airport. Once again, the leading-edge of on-chip interconnect technology developments were presented, with details on new materials, processes, and structures. 3D interconnects and through-silicon vias (TSV) were discussed in serious detail, while work continues on air-gap dielectrics and carbon nanotubes (CNT) along with new copper barrier materials.

3D with TSV may be considered as the ultimate interconnect concept, since stacked chips provide optimal functionality/volume, and provide for relatively low-cost heterogeneous integration of diverse technologies such as sensors. TSV and the many variations thereof have been hot topics in 3D for many years, with “via-last” being done today in production for memory stacks needing typically <100 TSV per chip. In contrast, “via-first” TSV processing flows may produce thousands per chip, and there are many integration schemes possible. IITC publicity chairman (and IBM researcher) Michael Shapiro commented that, “3D is such a ‘silicon-centric’ process technology that the IITC is really the place to have the discussion, because all the experts of silicon etching and planarization are here and have always been here.”

Fraunhofer IZM (Institute for Reliability and Microintegration) in Munich has been leading the world in 3D-IC work for over ten years, and researchers from there have been developing detailed system-level heterogeneous integration schemes for wireless applications (for the European 3D integrated sensor program “e-CUBES”). Their target is die-to-wafer (D2W) stacking of a tire pressure monitoring system (TPMS). The wafer has the microcontroller chips, onto which are stacked chips for the RF transceiver, pressure sensor, and bulk acoustic resonator (BAR). For TSV, they integrate chips with both solid metal trenches (typically W filled ~20 µm deep) or hollow vias coated with doped poly-silicon (through the 300 µm thick pressure sensor).

Researchers from Georgia Tech built upon work they first showed three years ago at IITC, and together with IBM and Nanonexus showed real results of using integrated microchannel cooling to remove heat from 3D-IC stacks. Fluidic microchannels were fabricated at the wafer-level using four lithography steps, and the resulting chips showed thermal resistance of just 0.24°C/W compared to 0.6°C/W for equivalent 65nm node air-cooled chips. With reduced thermal resistance, significant advances in speed, power, and/or operating temperature can be achieved; for example, power could be reduced ~20% at the same frequency, or the frequency could increase 10% at the same power.

Basic materials integration challenges of 3D integration were shown in two presentations by IMEC. Micro-Raman spectroscopy (µRS) was used to determine the plastic yield criterion for an accurate finite element modeling (FEM) of the stress near Cu-filled TSV. Due to the inherent mismatch between CTE of Cu (16.7 ppm/°C) and Si (2.3 ppm/°C), some strain will be inherent, and it may degrade electrical carrier mobility. Defining an “exclusion zone” of transistors from the TSV such that mobility degrades <5%,>
IMEC researchers also looked at reliability in a presentation on “Resistance to electromigration of purely intermetallic micro-bump interconnections for 3D-device stacking.” Both Cu-Sn and Co-Sn were shown to withstand 1000 hours of testing at the extremely aggressive conditions of 150°C and 0.63mA/µm2).

Scott Pozder of Freescale Semiconductor showed an excellent poster on Cu-Sn microconnects formed simultaneously with an adhesive dielectric bond using thermal compression bonding of flipped dice on a wafer. After D2W bonding using Cookson F602 material at micropad pitches of 59, 64, and 69µm, the robustness of the bond was shown by grinding the bonded dice to 50µm thin using a Disco Hi-Tec tool. While no TSV are used in this die-to-wafer stack, this pragmatic approach based on standard unit-processes which can be found in the open foundry market shows one clear way forward toward 3D today.

Tohoku University researchers showed one way to cut costs in D2W bonding: use a rough lithographic step to form hydrophobic and hydrophilic areas on the wafer, add an aqueous coating and then roughly place the dice. The surface tension of the liquid induces the dice to self-align, and control of the ambient can allow for the liquid to evaporate which temporarily bonds the dice to the wafer. The average alignment accuracy on 100 dice was ~0.5µm, with most dice aligned within <1µm and all <1.5µm.

D2W stacking of 3D chips allows for the used of known good dice (KGD) and the associated minimization of yield losses anticipated with wafer-to-wafer (W2W) stacking. D2W stacking technology will first follow Freescale’s lead by flipping the top die for two levels of silicon, but TSV and three or more levels will certain follow.

Much of the limitation in the use of TSV today remains with the designers; lacking EDA tools, it is not only difficult to optimize a design for 3D, it is challenging to just try to quantify the potential benefits in advance. Until EDA tools are ready the greatest potential value of 3D stacking will not be seen, and most commercial TSV will continue to be used for memory stacks and CMOS image sensors.

This is the last year in which interconnect technologists living in the San Francisco bay area have the exclusive luxury of the International Interconnect Technology Conference being local. Next year (June 1-3, 2009), the 12th IITC will occur in Sapporo, Japan at the Royton Sapporo hotel. The 2010 meeting will be back in the San Francisco bay area, and then the 2011 meeting is expected to occur somewhere in Europe.

—E.K.

Labels: 3D, IITC, interconnect, silicon, stack, through-silicon via, TSV

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080602: IITC shows the way to 3D

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Ed’s Threads 070928
Musings by Ed Korczynski on September 28, 2007

Who needs through-silicon vias?
Besides MEMS and opto-electronics, who really needs through-silicon vias (TSV) for commercial ICs? This was the burning question around which presenters danced for an afternoon at the International Wafer-Level Packaging Conference (IWLPC) held this September in San Jose, California. Starting with IC and wafer-level packaging technologies already in use, experts seem confident that technology integration can create a manufacturable TSV fab flow. However, while 3D-WLP is already commercially viable (pun intended), TSV do not seem to be needed for the near future; wire-bonding already can handle up to 16 chips, and 2 level connections can be easily flip-chipped for high-performance (like for a microprocessor cache).

Ken Gilleo of ET-Trends LLC discussed the “coming paradigm shift in packaging” caused by TSV and wafer-level packaging, asserting that significant technology development has occurred with unit processes in recent years such that the main technology hurdles remain with integration.

Leslie Lea, CTO and deputy CEO for STS, explained how deep reactive-ion etch (DRIE) for TSV on 300mm wafers will still use a derivative of the sequential “Bosch Etch” process, using the C4F8 plasma for polymer sidewall deposition, then SF6 plasma for etching. This process can produce vias to 80:1 aspect ratios, but sidewall scallops inevitably exist. Cu-TSV plating time shown was 4 hr for 50µm via, while 10µm via filled in 1 hr using NEXX systems and Enthone chemistry to create via fills without voids—with vias of 10-50µm depths all nicely filled on the same chip.

TSVs have been demonstrated in four different approaches and integration schemes: blind, poly, tungsten, and copper. Jim Walker, research vice president for Gartner Dataquest, suggests that we all should use the standard PCB term “blind vias” for essentially the same structures in silicon. Unlike the other three, ‘blind’ vias don’t include the conductor, but etch/drill out openings through an upper silicon chip, typically to allow a wire bonder to make connections to bond-pads on a lower silicon chip.

These are not new. Back in 1989 I developed a pilot process for a 3-level WLP using blind TSVs for an accelerometer chip for SenSym (Analog Devices’ designers were much smarter and their planar chip design was far more manufacturable and lower cost, so sadly for me at the time the chip was killed at pilot). Blind TSVs can be combined with flip-chip stacks and C4/C4NP bumping to get to three or more silicon layers with relatively low cost and minimal disruption of current packaging flows.

Blind TSVs are another way that wire bonders may continue to function as the ‘work-horses’ of packaging lines, working with KOH or EDPW wet-etches to form sloped openings along the crystalline planes in silicon. In an exclusive meeting with WaferNEWS, Giles Humpston, director of R&D for Tessera, explained that the company’s ~$100M investment in optical-WLP technology built on the acquired ShellCase technology for blind TSV applied to the unique requirements of image-sensors and quartz substrates.

Filled vias with poly, tungsten, or copper are the TSV ideal that many of us have conceived of for 3D ICs. If design and test software could handle it, and if integration can be as low as $200/wafer (EMC-3D goal), then these TSV might be first used to stack like devices like memory parts. Phil Marcoux, longtime packaging technology expert currently with Chip Scale/TPL Group, thinks that full integration won’t be ready for five years. Gilleo countered that in 2008, “some memory will use TSV.”

Citing first principles of electrical interconnection—going back to the use of copper in the first US printed circuit board patent in 1902—Gilleo is convinced that ultimately copper is the way to go for filled TSV. Used both for PCBs and on-chip interconnects, there is a tremendous amount of proven technology that can be borrowed to speed up TSV integration. “It’s well controlled in electroplating, and it has the right balance of chemical and mechanical properties,” informed Gilleo. It becomes the nature selection for the conductor. “It has almost everything you want for building conductor pathways.”

All of this was known to the early pioneers of the planar IC at Fairchild Semiconductor. And yet they chose aluminum over copper, because copper is more reactive and can more easily diffuse into silicon and damage transistors. Copper will always have a much higher expansion with temperature compared to silicon, and so high-temperature processes will inherently stress barrier layers. Polysilicon can be annealed and then have the same expansion with temperature as the silicon wafer. Of course, polysilicon conductivity is always lower than copper, so there are trade-offs in the TSV conductor choices.

While debating whether to consider integrating poly or copper or even tungsten plugs, a gold wire bonder has already made the connection. Packaging moves fast.

--E.K.

Labels: 3D, blind TSV, copper, IC, interconnect, stack, through-silicon via

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070928: Who needs through-silicon vias?

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