Ed’s Threads 080101
Musings by Ed Korczynski on January 01, 2008

2007 odds and ends
High-k (HK) and metal-gates (MG) for CMOS transistors are real and here now, with Intel deciding on HK-first but MG-last for process integration. What is the temperature limit for MG processing such that the HK remains amorphous in this flow, and how many other elements are alloyed with hafnium and oxygen in the final film? IBM and SEMATECH and most of the rest of the world seem to be working on HKMG-first integration.

IBM in the US has sold 45nm bulk silicon manufacturing technology to SMIC in the P.R. China. I remember being in Shanghai in 1995 when people in China talked about getting 250nm (then “quarter micron”) technology from US companies, and it was then deemed too powerful to let go; now such technology sells for pennies on the ever depreciating dollar. Meanwhile, Intel is reportedly still on schedule to open a 90nm logic fab in China.

Indian semiconductor fab plans seem to lack the political will needed to become real. An anonymous comment left on my prior blog entry about India's plans for its "Fab City" stated, “so far nothing happened. no electrical infrastructure and no water pipes. government is only fooling to promote the nearby real estate ventures.” Informal discussions with Indian expatiates at IEDM last month seem to confirm this perspective. The official Web site for the government now lists "Nano-Tech Silicon India Ltd." (NTSI) as a solar fab to be built -- just seven months ago the government insisted that it would soon be a 20K wafer starts/month IC fab. Despite delays in infrastructure, companies seem willing to try to start-up photovoltaic fab lines in India along with the rest of the world (scroll halfway down the page to see the list of promised PV projects).

With the price of oil nearly at US $100/barrel (less in other currencies), most of the world has decided that solar energy might be worth investing in for a while. Applied Materials continued to acquire its way into OEM dominance, while Oerlikon did a spin-out and acquired a top executive. (I recently talked shop with top PV execs at both AMAT and Oerlikon about their respective strategies.)

Meanwhile, subsystems suppliers like Advanced Energy and Edwards have shifted resources to follow the PV money. Nanosolar printed its first CIGS thin-film PV cells at its new line in San Jose, CA. HelioVolt announced its first fab to produce printed CIGS cells. Dick Swanson of SunPower gave a great presentation at IEDM (Session 14.1) on development of silicon solar cells, showing that manufacturing efficiency increases should cut final installed PV system costs 50% by 2012.

Never trust a semiconductor process engineer who isn't a great cook. It's all about recipes either way, and I've come to the unreasonable conclusion that all good process people like to play in the kitchen too. Baking holiday cookies reminds me of systematic yield losses and design-for-manufacturing (DFM) pattern-centric solutions -- in both cases you need uniform distribution of features across the surface to ensure uniformity. The more narrow the process window, the more you have to control repeatability across the cookie sheet (or silicon wafer).

From the wonderful people at the Annals of Improbable Research we get the yearly Ig Nobel Awards . My personal favorite award for 2007 -- due to love of Toscanini's Ice Cream -- is the award in chemistry given to Mayu Yamamoto of Japan's International Medical Center, for developing a way to extract vanillin from cow dung (REFERENCE: "Novel Production Method for Plant Polyphenol from Livestock Excrement Using Subcritical Water Reaction," Mayu Yamamoto, International Medical Center of Japan.) Moreover, kudos to Toscanini’s for creating a new ice cream flavor and introducing it at the Ig Nobel ceremony, called "Yum-a-Moto Vanilla Twist."

Speaking of twists, 2007 was also another year of consolidation across various equipment/process segments (Lam/SEZ, KLA-Tencor/Therma-Wave/FabSolve, Aixtron/Nanoinstruments, MKS/Yield Dynamics, and TEL/Epion to name just a few). Notable deals happened in the intersection of litho and design (Cadence/Invarium, Blaze/Aprio, and in late 2006 ASML/Brion), as well as test (Teradyne/Nextest, Verigy/Inovys, Rudolph/Applied Precision). Also, private equity had a major presence in the industry, particularly early in the year, in deals for Edwards' vacuum/equipment biz, backend firms STATS ChipPAC, UTAC, and UK dep/etch firm STS. And even AMD looked overseas for much-needed external funds.

One surprising end to 2007 was the Republic of Lakotah formally withdrawing from all treaties with the United States of America, and reclaiming sovereignty as a nation and over its traditional grounds. Maybe someone can build an IC fab there.

After Motorola's advanced fabs became Freescale and then moved R&D to France and then New York, and after Texas Instruments decided to end R&D at 45nm, and after the Silicon Valley Technology Center (Cypress’ former R&D fab) bought the Advanced Technology Development Fab, it’s time to pause for a moment of silence. SEMATECH in Texas is dead; long live SEMATECH in New York!

— E.K.

Labels: CMOS, consolidation, Fab City, HK+MG, photovoltaic, SEMATECH

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080101: 2007 odds and ends

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Ed’s Threads 071211
Musings by Ed Korczynski on December 11, 2007

It’s time for IEDM, and ~1600 leaders of the CMOS fab world have gathered in Washington D.C. to announce the latest, greatest in new devices. The first big news concerns high-k/metal-gate (HK+MG) transistors for 45nm node and beyond processing. With many parallel sessions covering the most important technology trends in IC manufacturing, it is impossible to mention all of the great results presented by teams from around the world (apologies to: ST/NXP/Freescale, Fujitusu, MIRAI, NEC, SELETE, Sony, Toshiba, and TSMC).

Presenting on behalf of 53 co-authors, Intel VP Kaizad Mistry disclosed some real details of the company’s latest 45nm process technology featuring HK+MG. Finally answering the gate-first or gate last question with “both,” Intel has decided that the tough integration challenges for high performance logic can be best met with HK first but MG last processing. The transistors feature 1.0nm equivalent oxide thickness (EOT) dielectric, based on an atomic layer deposition (ALD) of a hafnium-based compound -- no additional details yet on other elements likely to be used in this ALD step, whether the phase of the final material is amorphous or crystalline, or what is the specific interface from the HK to the highly-strained channel. (In a side conversation after Mistry's talk, Intel Fellow Tahir Ghani confirmed the need for this interface, but would provide no details, only noting that it is critical for mobility.) pMOS performance is improved by increasing the Ge content of the embedded SiGe to 30% (from 23% @ 65nm, and 17% @ 90nm) and by reducing SiGe proximity to the channel. Lithography utilizes 193nm dry patterning, though some masks require two exposures in two resist layers along with a sacrificial hardmask. Transistors feature 35nm physical gate length, ultra-shallow junctions, and nickel silicide. Drive currents are benchmarked at 1.0V, a low 100nA/μm I_OFF and at 160nm contacted gate pitch. pMOS drive current of 1.07 mA/μm (51% improvement over 65nm), while nMOS drive current is 1.36mA/μm (12% better than 65nm). SRAM arrays with cell sizes of 0.346μm² and 0.383μm² (performance dependent) and multiple microprocessors are already in volume production, with claimed excellent yields.



Figure. TEM micrograph of 45nm Intel high-k + metal gate pMOS transistor. (Source: IEDM2007 10.2)


Intel’s gate-first/last HK+MG process flow for 45nm transistors is as follows:
- STI, well, and V_T implants,
- ALD (18-20Å) of HK gate dielectric,
- Polysilicon deposition and gate patterning,
- Source/drain extensions, spacer, Si recess and SiGe deposition,
- Source/drain anneal, Ni salicidation, ILD₀ deposition,
- Poly opening CMP, poly removal,
- pMOS work-function metal deposition,
- Metal gate patterning, nMOS work-function metal deposition, and
- Metal gate Al fill and Al CMP, etch-stop layer deposition.

IMEC and its partners (TSMC, Matsushita, Infineon, Samsung, and NXP) showed a low V_T CMOS gate-first HK+MG using TaC-based metals and laser-only annealing. Symmetric low V_T values of ±0.25V and unstrained I_DSAT of 1035/500μmA/μm (for nMOS/pMOS respectively) at I_OFF=100nA/μm and VDD=1.1V were demonstrated on a single wafer. To do so required Hf-based high-k dielectric capping layers of lanthanum oxide (La₂O₃) for nMOS and aluminum oxide (Al₂O₃) for pMOS to lower EOT from ~17 to ~15 while maintaining the same target V_T. HK-caps in combination with a laser-only activation anneal maintain band-edge equivalent work-function (EWF) and minimal EOT re-growth. La₂O₃ thickness control allows for V_T turning from 0.2 to 0.6 for nMOS. HfSiO shows lower V_T and higher mobilities compared to HfSiON. The laser-only anneal further results in improved L_G scaling of 15nm and a 2Å T_INV reduction over the spike reference. Lam etchers were used for gate patterning. IMEC has also been working on HK+MG for finFETs.

Prof. A. Toriumi et al. (U. of Tokyo, MIRAI-AIST, MIRAI-ASET) presented on “Materials Science-based device performance engineering for metal gate high-k CMOS.” EOT is based on k, which is based on the internal field and the polarizability of the material itself. HfO₂ has monoclinic phase, but adding lanthanum, silicon, yttrium, and/or titanium can change the phase to cubic or tetragonal, while the k increases to ~30. Adding La₂O₃ increases the crystallization temperature up to 800-1000°C (over the range of 20%-40% incorporation), and the amorphous phase has the best overall properties. Regardless of composition, leakage current depends only on the physical thickness, which shows that the leakage mechanism is pure direct tunneling. Thus, using higher-k films with equal EOT (down to ~0.5nm) significantly reduces the leakage. Flat-band voltage shift has been clearly shown to be determined only by the dipoles formed at the bottom interface between SiO₂ and HK, and not by the HK to MG interface. Scattering effects should be correlated to both the material itself and oxygen vacancies in the material.

Important information is being learned about nMOS/pMOS boundaries, according to H. Rusty Harris from SEMATECH, who gave an amazing presentation on a “Flexible, simplified CMOS using HK+MG on Si(110). “What we have shown is that if we add capping layers on top of the dielectric we do not see mobility degradation,” he said. Carrier mobilities depend upon crystallographic orientation, and changing from standard (100) to (110) orientation allows for mobility increase of 3X for holes, while electron mobility drop by ~1/2. Mixed orientation -- Si(100) for nMOS, and Si(11) for pMOS -- has been examined but process complexity, cost, and variability seem unattractive. Data for Si(110) planar CMOS is relatively similar to multiple orientation approach (with much lower manufacturing cost), though an pre-amorphosizing implant is used to minimize diffusion which is faster in (110) compared to (100) silicon. Even better results should be seen with finFETs, which inherently require orientation engineering. Using large 0.25μm planar transistor lengths (not short enough to fully realize the nMOS improvements), they showed that ring oscillators were nearly equivalent regardless of (110) or (100). Sub-threshold leakage is an important factor in LSTP optimization, and gate-induced drain lowering (GIDL) is the second biggest factor in off-state power. Without even optimizing the process flow for (110), using (110) lowered GIDL by an order of magnitude compared to (100).

CEA-LETI-MINATEC/Soitec use TiN metal over HfO₂ HK gate dielectric to explore the limits of HK+MG with SOI substrates. From a historical perspective, Takagi et al. (IEDM '97) showed that long-channel transport conditions effectively degrade electron mobility as dielectric thickness decreases. Gate lengths from 18nm to 10μm were fabricated, all with widths of 10μm, EOT 1.7nm, and 145nm BOX thickness. They consider ballistic carriers may primarily determine the conduction in sSOI short-channel devices, and invoke a “ballisticity rate” to partly explain the influence of surface roughness scattering. Si thickness down to 2.5nm for SOI has been used for both HP (I_On=780ΜMA/μm) and LP (I_OFF=10pA/μm) devices.

Meanwhile, IBM and its partners missed out on getting a HK+MG paper into IEDM this year, and instead issued a press release about 32nm development. Having publicly committed to gate-first processing, Freescale researchers in the alliance have published a paper in the Journal of Applied Physics on the crystalline phases formed using zirconium along with hafnium-oxide. Hafnium zirconate (HfZrO₄) alloy gate dielectric and hafnium dioxide (HfO₂) films were formed by atomic layer deposition using metal halides and heavy water as precursors.

–E.K.

Labels: ALD, future, high-k, HK+MG, IBM, Intel, metal gate, transistor

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071211: HK+MG real details shown at IEDM

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Ed’s Threads 070720
Musings by Ed Korczynski on July 20, 2007

HK+MG metrology technology
With High-k (HK) dielectrics and metal-gates (MG) now being ramped into CMOS production at Intel and IBM, much of the excitement at the just finished SEMICON West 2007 in San Francisco centered around manufacturing technologies needed for these new materials. ASM and Imago sponsored seminars on these topics, and much of the discussion in panel discussions sponsored by Praxair and DuPont centered on the challenges of working with these new materials. In particular, setting up affordable in-line metrology for these new ultra-thin materials will be tricky.

Recently departed SEMATECH Fellow Alain Diebold, now a Professor at the U. Albany, provided an overview of the need for HK metrology in a breakfast seminar sponsored by Imago. For HfxSi1-xO2, both x=0.25 and 0.75 are stable structures, which may be regarded as Hf substituted in an SiO2 matrix and Si substituted in an HfO2 matrix, respectively. HK layers in production will likely be just 3-5 atomic layers thick. Since improving hole mobility is inherently difficult, one first possible application of finFETs is to integrate PMOS finFETs with planar nFETs at the beginning of the 32nm node. “We need atom-by-atom characterization and metrology for fins in R&D; today, not later,” informed Diebold.

The U. of North Texas—previously renowned for its jazz music scholarships—inherited an old TI fab and received $11M in funding to invest in cutting-edge metrology tools. TEM can resolve sub-angstroms spatially, but chemical resolution is limited to ~1%. Secondary ion mass spectroscopy (SIMS) provides sub-parts-per-million chemical resolution, but lacks special resolution. Local-electrode atomic probe (LEAP) systems sold by Imago Scientific Instruments provide ~2Å spatial resolution and ~E18 chemical resolution, using full-width-half-maximum (WFHM) measurements of a calculated concentration curves to calculate thickness. Approximately 80nm diameter silicon samples are cut from wafers using a dual-beam FIB, and 6-7 samples can be prepared in an hour by a skilled FIB operator. Dopant “snow-plow” effects in diffusion, quantum well structures, and buried interface roughness can all be analyzed to calibrate in-line metrology techniques. LEAP reconstructions of this HK stack as-deposited and post-anneal show 0.5nm of Hf and O diffusion.

Since LEAP provides excellent resolution but is inherently destructive and relatively slow, it is ideal for R&D; but cannot be used for in-line production control. Still, LEAP and other lab techniques are vital for calibration of production control approaches. “The type of information that you get from R&D helps you set up your in-line metrology, and the two work hand-in-glove, as Howard Huff used to say,” reminded Diebold. With HKMG now ramping in production, there’s a crop of new in-line metrology tools available.

ReVera provides XPS tools that can resolve thickness, composition, profile, and chemical bonding states information from thin dielectric films, and claims customers are using the tool to measure gate-dielectrics and HK storage for memory chips. XPS can measure all elements heavier than He for any film or material up to 100Å thick in any part of the process flow.

After one year of promoting it for high-volume metrology applications such as HK+MG, Metryx claims sales have doubled for its mass monitoring tool, which has sufficient resolution to detect differences in the atomic masses between silicon (28 g/mole) and hafnium (178 g/mole) in hafnium-silicate ALD layers. The company claims wins with customers for process control applications in volume fabs, typically measuring the masses of >60 wafers/hr.

Metrosol’s vacuum ultra-violet (VUV) spectroscopic reflectometer was designed specifically to handle in-line metrology of ultra-thin dielectrics. Two manually-loaded chambers have been in use for over two years at customers, one for hafnium-silicon-oxide films and one for nano-imprint lithography (NIL). The first five beta units of the fully-automated tool will be ready this September. The purchase cost is claimed to be 1/2 to 2/3 of an x-ray or extended range ellipsometer, and typical throughputs are 2x-10x of such systems. (Click for WaferNEWS' interview with CEO Kevin Fahey.)

Since thin-film metrology is pointless if you can’t deposit the material in the first place, the readiness of the industry to begin volume production of chips using HK gate-stacks has been shown by ASM officially releasing its Pulsar ALD chamber for the company’s Polygon cluster-tool. ASM likes to term its ALD variant atomic-layer CVD (ALCVD), though the process and hardware seem quite similar to other single-wafer ALD technologies.

Gate-first HK stacks use a capping layer such as lanthanum-oxide to form a dielectric dipole in the vertical dimension. This cap oxide is hygroscopic, so the stack should be formed without breaking vacuum to eliminate exposure to water vapor. This is just one of the critical integration issues which must be controlled in the formation of HK+MG CMOS transistors. With atomically thin films and complex interdependencies in integration, the “make versus buy” decision for 2^nd-tier fabs will almost certainly fall to buying it, because it just cannot be easily made. “Even if you reverse-engineer the chip, you can’t discern the integration scheme,” explained Glen Wilk, product manager for transistor products at ASM.

Don’t worry if all of this sounds almost too difficult to manage. Professional materials scientists have been working on the research for decades, and we’re now in the era of engineering specific solutions to known problems. Stay tuned for yearly breakthroughs.

—E.K.

Labels: ALCVD, ALD, high-k, HK+MG, LEAP, manufacturing, metrology, XPS

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070720: HK+MG metrology technology

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Ed’s Threads 070615
Musings by Ed Korczynski on June 15, 2007

IBM HK+MG gate-first processing
At the VLSI Symposium on June 14th, and after months of a mainstream press hype-war with Intel, IBM finally unveiled some of the details of its new high-k/metal-gate (HK+MG) transistor technology. Mukesh Khare, IBM project manager for high-k/metal-gate development, presented integration details of the new transistors while keeping specifics of materials and processing confidential. The key information is that their HK+MG “gate first” approach keeps the same processing sequence used by traditional SiON gates, allowing for both technologies to be run on the same line and minimizing integration costs.

“We did a lot of work to look at gate-first and gate-last, and both approaches have challenges,” explained Khare, in an exclusive interview with SST and WaferNEWS. “We picked the approach that is simple, scalable, and also migrate-able.”

Gate-first is simple in terms of changes to existing processes, and looks scalable to smaller device geometries. “Migrate-able” means making it easy to port designs from SiON transistors. Indeed, gate-first processing seems to be the best overall approach -- if you can find a material that can withstand the high temperatures used in device annealing. Keeping most of the existing process flow intact, 45nm will still use tungsten plugs for contacts.

Transistor formation typically requires ~1000°C annealing to allow atoms to settle into proper places after ion-implantation, which inherently damages silicon crystals. Any gate materials in place during annealing must withstand such temperatures without losing their properties. In particular, the high-k dielectric material must maintain a certain composition and material phase to ensure that the transistors do not leak current.

All IBM will officially say to date is that its gate-first high-k material is hafnium-based, which is the currently known default standard, but they will not yet specify anything else. The material is likely to be a blend of hafnium, silicon, oxygen, and nitrogen, which can be seen as just adding the hafnium to the SiON currently used. Hafnium atoms have a relatively higher oxygen coordination number and are simply larger (atomic number 72, compared to silicon at number 14, and oxygen and nitrogen at 8 and 7, respectively), so adding them to the SiON currently used increases the dielectric constant of the layer based on density functional theory. The thickness of the inversion layer under the gate (Tinv) with conventional oxynitride is typically, at best, 18-19 Å -- IBM’s HK+MG transistors reportedly demonstrate Tinv ~12Å, something achieved, by working for over 10 years on fundamental materials engineering.

Though not needing any fundamentally new metrology techniques, every film will require control. For example, compositional changes with nitrogen depth have already been used with nitrided-oxide gates (SiO:N), so one possibility is a nitrided-hafnium silicate (HfSiO:N). Nearly all the recent HK dielectrics that have been shown for CMOS transistors have been stacks of layers with atomic-level engineering of the interfaces. The specific composition and gradients within the layers are officially secret, but it is highly likely that there is at least one atomic layer of SiO at the bottom.

HK+MG transistors at nanometer-scale nodes are constrained by the same trade-offs between speed and leakage (for HP or LSTP circuits, respectively) as with SiON+poly transistors. Engineering the dielectric stack to be either fastest/leaky or fast/tight for a target HP or LSTP, there’s a single HK gradient-stack and one metal used for both NFET and PFET gates. Poly-silicon tops the metal gates. “After more than three years on the 300mm pilot line, there’s been a lot of learning and we’re on track,” Khare noted.

For planar devices, there are more options in terms of ALD, CVD, or PVD, explained Khare. He claims that the cost to use HK+MG is similar to that needed for any new technique like using a dual-stress liner, and so it adds minimal additional cost to the final wafer, but not all designs will need the performance improvement so some chips at 45nm and 32nm will still use SiON+poly. “It depends on the product needs. It is a very powerful technology. It’s very simple,” stated Khare. “The materials challenge was very high k, and that’s one thing we focused on.”

—E.K.

Labels: CMOS, high-k, HK+MG, IBM, metal gate, transistor, VLSI

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070615: IBM HK+MG gate-first processing

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Ed’s Threads 070129

Musings by Ed Korczynski on January 29, 2007


Intel wins race to be Intel
How did it happen? How could Intel present 45nm transistor results with high-k dielectrics and dual metal gates (HK+MG) years ahead of everyone else? Mark Bohr, Intel senior fellow in logic technology development, stated, “I don’t believe any other company will have high-k and metal gates until the 32nm node or later.” If this is true, it is only because IBM and other companies felt that they wouldn’t need HKMG for 45nm so they did not start manufacturing work two years ago. Thus, Intel has won a very difficult race as the single contestant.

It seems that the company even surprised itself with these results. On Thursday Jan. 25th, the day before the official announcement, Intel invited journalists to a last-minute show-and-tell at its Robert Noyce HQ building in Santa Clara, CA. PCs running on 45nm “Penryn” chips were shown—all of which came from the “first-silicon” wafer with these new materials processed using the first mask-set. Packaged first-silicon chips received at Intel’s Folsom test lab at 1:00 am had functioned, and the team immediately rushed one into a motherboard which promptly booted a software OS two hours later. Intel showed a photo of the team toasting their success with Martinelli’s sparkling cider at 3:00 am—give Intel credit for maintaining entrepreneurial zeal with nearly 100,000 people.

Two core competencies were at work to get to these results: extreme discipline in manufacturing execution, and proprietary design and yield-learning methodologies. Since Intel has always had to live in the brutal merchant market, it has always aimed for the sweet spot in the middle of manufacturing-cost and chip-performance, and then relentlessly driven to meet its goals. Instead of silicon-on-insulator (SOI), Intel pushed traditional planar transistors on bulk silicon wafers to the limits of traditional materials for its current 65nm node manufacturing.

Looking at 45nm options about two years ago, Intel decided to stick with bulk silicon wafers and add HK+MG. In Jan 2006 it announced yielding SRAM TEG chips with >1B transistors, but kept secret that these chips used HK+MG. Still secret is the hafnium-based dielectric composition, both of the metal gate materials, and whether the process flow is “gate-first” or “gate-last.” The new transistors still maintain strain in the channel regions for maximum carrier mobility. Innovative design rules and advanced mask techniques will be used to extend the use of 193nm dry lithography, which we may assume includes orientation limitations in harmony with illumination sources. All these changes result in new process integration challenges and new yield-loss mechanisms, so we might expect it to take a while longer to ramp yield. Amazingly, Intel shows a 45nm yield-learning curve that tracks the last three nodes (see figure, above).

CEO Paul Otellini—dressed all in black like an international jewel thief, perhaps due to having spent excessive time around Steve Jobs—stated, “The plan is to have microprocessors in end-users hands by the end of 2007.”

Meanwhile, with timing that just could not be coincidence, on January 26th SEMATECH announced R&D; of a gate-first HK+dualMG process. “Be aware of the difference between a real manufacturing commitment, and research papers that continue to fall short of these results,” stated Intel's Bohr. The very next day IBM/AMD/Sony/Toshiba said that they will use HK+MG with their 45nm transistors sometime in 2008. We may assume that this announcement was rushed out in response to the Intel press release, since it erroneously refers to HK+MG as a single material—either the IBM alliance plans to use only one of the two, or IBM needs a technologist to review their press releases.

Technology development continues in the industry. Intel’s use of HK+MG materials in mainstream 45nm commercial manufacturing is certainly a significant milestone. Certainly other companies will follow, though in their own ways and in their own times. Due to the extreme complexities involved in any nanometer-era IC manufacturing, it’s getting more and more difficult to compare results from different companies. Fortunately, you can trust SST and WaferNEWS to sort the reality from the hype.

— E.K.

Labels: 45nm, high-k, HK+MG, IBM, Intel, metal gate, semiconductor

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070129: Intel wins race to be Intel

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