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080317: There is no more noise...
Ed’s Threads 080317
Musings by Ed Korczynski on March 17, 2008

There is no more noise...
There is only signal. In controlling the manufacturing processes used for advanced nano-scale IC, the aspects of metrology which we used to be able to ignore as “just noise” are now essential signal we must control. Where to draw the line, and how close is close are just some of the challenges in ensuring that data streams become productive information for fabs. Metrology sessions at SPIE this year shone fractional wavelengths of light into the darkness of controlling accuracy, too.

When IC features were greater than the wavelength of light used in photolithography—and likewise much greater than a countable number of physical atoms—there were many aspects of manufacturing which we could simply ignore. With the smallest IC feature, typically defined by the minimum half-pitch spacing between lines, now reaching ~45nm (which is less than one-quarter of the 193nm wavelength used in litho) we now experience “second-order” and “third-order” effects which must be controlled.

Vladimir Ukrainstev of Veeco Instruments co-led a panel discussion at SPIE 2008 on the need for CD-SEMs to be accurately calibrated with 3D-AFMs. Researchers have reportedly seen a mere 1° change in the sidewall angle of a device structure result in a 2nm change in the CD measured by a standard 2D SEM. With the allowable budget for CD variation shrunk down to 3nm-4nm, this sidewall angle dependence must be controlled. The greatest risk is in process drift in an etch chamber, where sidewall angle can change spacially (e.g., from the center to the edge of wafers) or temporally (from wafer to wafer over time), which can induce substantial error in the CD-SEM measurement.

With tight feedback loops in advanced fabs, erroneous CD-SEM data can be mistakenly used to set the wrong etch parameters for following lots, which can degrade yield. “Instead of changing CD etch time by the week, we’re changing by the lot or the wafer as part of APC,” explained Kevin Heidrich, Nanometrics’ senior director of new business development, in an exclusive interview with WaferNEWS. Total CD control is ~4nm for all variability; a normal rule of thumb for precision over tolerance is 0.1, so the total budget for metrology is 0.4nm.

All measurement techniques are subject to some error, and even the best 3D-AFM is still subject to tip-wear and calibration. Veeco has been working with 3rd-party specialists to optimize AFM tips for different applications, with great results reported for various shapes nano-machined from single-crystal silicon for strength and then coated with some manner of a carbon coating for wear-resistance. NIST showed SPIE attendees this year that even with a slow, expensive, and destructive technique like TEM, there is still 0.33nm (standard deviation, 1σ) of the sidewall angle uncertainty. Everything else adds up to 0.63nm of total uncertainty. Calibration is vital to minimize the propagation of uncertainties.

One of the issues in determining the side-wall angle is what portion of the sidewall to include in the analysis. For features with corner rounding, this could be challenging even with ideal 90 degree sidewalls. Just considering 2nm radii of curvature on the top corners of etched polysilicon lines of 32nm to 45nm widths, and ~10% of the linewidth varies with where a CD-SEM draws the line for the edge.

To help control APC in all manner of deposition and removal processes, Nanometrics recently announced the delivery of the company’s 1000th integrated metrology sub-system; the milestone system was integrated into an advanced plasma etch system used to control gate CD in advanced logic devices.

At SPIE, IBM (Daniel Fischer et al.) showed OPC requirements for 32nm and the metrology tool calibrations need to support this advanced node. Modeling calibration sites per mask level has increased dramatically: normalized to the 90nm node, 65nm had 10×, and 32nm is 100×. There are now multiple CDs per contour, which results in a reduced number of measurement sites per wafer. For tool calibration, fundamental parameters of magnification, rotation, etc. each must be properly considered in modeling. The researchers showed that scanning a line array in orthogonal directions in a CD-SEM induced up to 2% variation in measurement due to the beam’s oval shape. It’s not noise anymore. “The users must understand the measurement techniques and have them constant or have a consistent offset to be able to use the data,” said Fischer. He added that with real device structures, 144nm was seen by a 2D tool while 160nm was measured by a 3D tool, so some manner of rigorous automated edge-detection is essential.

OCD looks very extendable to finFETs, too. SEMATECH and KLA-Tencor presented a paper on metrology for high-k finFETs at SPIE. Using high-k HfSiO thicknesses of 1.5nm and 3nm over Si3N4, and using TiN as the metal gate, a thorough DOE of depositions over fins was done. Then using KLA-Tencor's next-generation spectroscopic ellipsometer (measuring 225nm and up) for OCD, and CD-SEM from AMAT and also HR-TEM, cross-checks between the OCD and standard thin-film measurements showed that the offset was ~1nm. For the metal gate measurements, it was found that the TiN optical properties varied due to what is suspected to be some manner of slight oxide formation. Data from dense arrays showed serious offset from the pad areas, so correlations must be considered. Measuring in the fin area seems to provide sufficient resolution for process control for both the high-k and metal-gate depositions. OCD measurement precision was at the 1% level or better, and in good agreement with reference measurements. OCD looks very promising for finFET gate stack characterization.

n&k Technologies has modified the optical path of their spectroscopic ellipsometer tool to add a pinhole lens which narrows the transmitted beam spot size from 400μm to 50μm. Since real-world ICs and photomasks tend to have designed areas with regular 50μm arrays, this opens up the ability to measure many more real structures. Collecting the reflectance and transmission in both s- and p-polarizations using 50μm spots provides four separate signals to be used in determining all the layer thicknesses on the mask, including quart etch dimensions for phase-shift masks.

In pushing the limits of signals, IBM and Hitachi recently announced a unique, two-year joint semiconductor metrology research agreement for 32-nm and beyond characterization and measurement of transistor variations. Engineers from the two companies and Hitachi's subsidiary, Hitachi High-Technologies, will conduct joint research at IBM's Thomas J. Watson Research Center in Yorktown Heights, NY and at the College of Nanoscale Science and Engineering's Albany NanoTech Complex. Combining individual research strengths and IP will help "reduce the significant costs associated with research needed to advance the next generation of chip technology," said Bernie Meyerson, VP of strategic alliances and CTO for IBM's systems & technology group, in a statement.

Rudolph Technologies has become the first OEM to join SEMATECH's Metrology Program headquartered at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany. The initial program addresses a range of issues, including the metrology of thin films and metal gate stacks; wafer front, back, and edge macro defect inspection; and inspection and metrology for through silicon vias (TSV) and three-dimensional integrated circuits (3DIC).

-- E.K.

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070914: Missing micrograms and measurement accuracy
Ed’s Threads 070914
Musings by Ed Korczynski on September 14, 2007

Missing micrograms and measurement accuracy
The “one true” kilogram cannot be trusted anymore. All standards must be based on a reference, and the master reference for mass on planet earth is a platinum-iridium-alloy cylinder kept in a special vault in Sevres, southwest of Paris. The 118-year-old master cylinder now appears to have lost 50µg compared with the average of dozens of copy-masters, and the reason is a mystery. "They were all made of the same material, and many were made at the same time and kept under the same conditions, and yet the masses among them are slowly drifting apart," said Richard Davis of the International Bureau of Weights and Measures in Sevre, France. "We don't really have a good hypothesis for it."

Each copy-master, officially termed a “National Prototype,” is used as the main reference in different countries (the Figure shows the US National Prototype Kilogram, held by NIST) to calibrate measurement systems. Scientists tend to care that a kilogram is absolutely a kilogram. Engineers tend to care that they get about the same amount of something every time, relatively speaking. The difference is between “accuracy” and “precision” in measurements.

Accuracy is defined as how closely a measurement matches an actual or “true” value, while precision is the repeatability of multiple measurements. How we can ever really determine the true value is another question.

The real world of our experience is never “ideal.” The surface of our planet is hot enough that random kinetic energy within atoms as lattice vibration induces finite vapor-pressure so solids may alter and be altered by their environment. Thus the act of measurement may alter that which is being used to measure, which is not a macro-scale variation on Heisenberg’s Uncertainty Principle, but an honest acceptance of the fact that macroscopic solid surfaces interact with their environments. Copies and redundancy may be used to detect any such drift of mass, and this is where we now find a problem—either the copy-masters accreted mass due to some as-yet-inconceivable phenomenon, or the master lost mass. Neither scenario is easily explained.

How might this possible loss of an absolute mass reference effect semiconductor manufacturing? Though chip fabs use technologies in common with other industries such as specialty gases and vacuum pumps, relative references are sufficient. Based on the inputs, engineers always “center processes” which then become relative standards. "Copy Exactly", as defined and developed by Intel, fully embraces this concept; once an input is proven in manufacturing, external references may be ignored. As long as a process is very reproducible—precisely—it’s accuracy can be relative.

Absolute standards just aren’t essential for this industry to test chips before shipping them to customers either. Digital chips are designed to functions as circuits of binary units, so a slight shift in internal relative values wouldn’t matter. Even analog chips or sensors are still designed to typically allow for calibration of some sort, so for example the gain could be tweaked to allow for a drift in a basic parameter. Given the inherent variability of batch processing with the need for consistent IC functionality, the industry has learned to handle slight shifts in parameters.

So, we can all relax and not worry about our industry losing its way if “The kilogram” has lost 50 parts-per-billion (ppb) of mass. Companies such as Process Specialties Inc. and VLSI Standards still provide “NIST-traceable reference standards” for the industry, which are more than adequate for our needs. What more can be done?

For over two years now, NIST and other standards groups have advocated for a kilogram standard based on something beyond a physical master, though more work is needed. One option would be to assume Avogadro’s constant (the number of atoms in a mole of matter) and then measure spacing in a “perfect crystal” to determine the number of atoms in a reference mass. Another option would be to count the number of electrons flowing through superconducting coils needed to balance a mass accelerated by gravity. “Currently, both methods are 10-100x less precise than the measurement uncertainty produced when comparing the kilogram artifact to national standards,” according to consensus from the Royal Society of London.

Supposedly, one of the leading alternatives for a 21st-century kilogram is a sphere made out of a Silicon-28 isotope crystal, though to the best of my knowledge any macro-scale crystal made up of gazillions (a technical term) of atoms on the surface of planet earth (with temperature ~298°K resulting in “random” energy) will have defects. The lattice spacing may be uniform and measurable, but vacancies and defects will still exist. These are some of the issues associated with pushing the limits of physical standards.

Humans have imagined absolute standards for thousands of years. Just like the conceived Platonic Solids, however, absolutes don’t exist in the real world. So we can keep dreaming of perfect standards, but back in reality we’ll still be counting exceptions and measuring variations.
–E.K.

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Ed's Threads is the weekly web-log of SST Sr. Technical Editor Ed Korczynski's musings on the topics of semiconductor manufacturing technology and business. Ed received a degree in materials science and engineering from MIT in 1984, and after process development and integration work in fabs, he held applications, marketing, and business development roles at OEMs. Ed won editorial awards from ASBPE, including interviews with Gordon Moore and Jim Morgan, and is not lacking for opinions.